Freescale Semiconductor,inc.

Nxp Usa, Inc.

Wei Gao

Zhiwei Gong

Dehong Ye

Scott M Hayes

Jinzhong Yao

William H Lytle

George R Leal

Craig S Amrine

Jianwen Xu

Huchang Zhang

Jinsheng Wang

Lizabeth Ann Keser

Yanting Tian

Nageswara Rao Bonda

A method of fabricating a 3D fan-out structure for an integrated circuit device includes providing a substrate carrier having first and second opposing surfaces and an aperture extending between the first and second surfaces. A first semiconductor die is bonded to the first surface of the substrate carrier such that the first die covers the aperture of the substrate carrier. An encapsulant and a second die are deposited within the aperture of the substrate carrier such that an active surface of the second die is exposed and coplanar with the second surface of the substrate carrier. One or more redistribution layers are then applied on the second surface of the substrate carrier to form a 3D fan-out structure.

Method of fabricating 3-dimensional fan-out structure

A package substrate having an opening and through-substrate interconnect structures is attached to a temporary carrier such as an adhesive film. The active surface of an IC die is placed in contact with the carrier substrate within the opening, to temporarily attach the die to the carrier substrate. Another die is attached to the side of the first die furthest from the carrier substrate. In one embodiment, the dies are attached to each other using an epoxy so that their respective non-active surfaces face each other. Bond wires are connected between interconnects at the active surface of the second die and the substrate. The wires are then encapsulated. After removal of the carrier substrate, a build-up interconnect structure is formed that includes external interconnects of the package substrate, such as solder balls of a ball grid array package.

Method of packaging integrated circuit die and device

A semiconductor device assembly includes an interposer having an opening extending from a first major surface to a second major surface of the interposer and a plurality of external connectors on the second major surface. The first major surface of the interposer is attached to a packaged semiconductor device. The opening of the interposer exposes the packaged semiconductor device.

Apparatus and methods for multi-die packaging

A method of forming a semiconductor device assembly includes forming an interposer having an opening extending from a first major surface to a second major surface of the interposer and a plurality of external connectors on the second major surface. The method further includes attaching the first major surface of the interposer to a packaged semiconductor device, wherein the opening of the interposer exposes the packaged semiconductor device.

An integrated circuit package has an exposed die pad with a trench and openings in the trench that are filled with encapsulant to form an encapsulant ring near the edges of the die pad. During assembly, the encapsulant passes through the openings and fills the trench to form the encapsulant ring. The ring helps to keep the die pad from separating from the encapsulant caused by thermal cycling. Air vents might be included in the die pad surface to allow air to escape from the trenches and the openings as they fill with encapsulant. Trenches from the openings to the die pad edge on the chip-side of the die pad might be included to increase adhesion of the encapsulant to the die pad.

Exposed pad integrated circuit package with mold lock

Methods for forming electronic assemblies are provided. A device substrate having a plurality of electronic components embedded therein is provided. The device substrate is attached to a carrier substrate using an adhesive material. A plurality of cuts are formed through the device substrate to divide the device substrate into a plurality of portions. Each of the plurality of portions includes at least one of the electronic components. A force is applied to each of the plurality of portions in a direction away from the carrier substrate to remove the plurality of portions from the carrier substrate.

Method for singulating electronic components from a substrate

A method for fabricating a semiconductor package is disclosed that includes providing a supply of lead elements, mounting a plurality of the lead elements on a lead frame until a predetermined number of lead elements are placed on the lead frame, and connecting other components on the lead frame to the lead elements.

Apparatus and methods for quad flat no lead packaging

A method of forming a semiconductor device includes affixing a die to a heat sink to form a die and heat sink assembly and then placing the die and heat sink assembly on a support element. A semiconductor device includes a die and heat sink assembly disposed on a support element. The die and heat sink assembly is pre-assembled prior to being disposed on the support element.

Semiconductor devices and methods of assembling same

A method and apparatus are described for fabricating a low-pin-count chip package () including a die pad () for receiving an integrated circuit device and a plurality of connection leads () having recessed lead ends () at the outer peripheral region of each contact lead. After forming the package body () over the integrated circuit device, unplated portions () of the exposed bottom surface of the selectively plated lead frame are partially etched to form recessed lead ends () at the outer peripheral region of each contact lead, and the recessed lead ends are subsequently re-plated () to provide wettable recessed lead ends at the outer peripheral region of each contact lead.

Growing community of inventors

Tianjin, China

Wei Gao