Silicon Integrated Systems Corporation

Wei Feng Lin

Chung Ju Wu

Wen-Yu Lo

Wen-Dong Yen

Kuei Chen Liang

A substrate used in a semiconductor device. The substrate includes a first wiring layer, a second wiring layer, and an interconnection-wiring layer. The first wiring layer includes a plurality of first pads, and the second wiring layer includes a plurality of second pads. The interconnection-wiring layer is set between the first and second wiring layer. In this case, at least one of the second pads that does not electrically connect to anyone of the first pads electrically connects to the interconnection-wiring layer. In another case, a shielding portion, which electrically connects the interconnection-wiring layer, is provided around the second pad that doesn't electrically connect to anyone of the first pads. Furthermore, this invention also discloses a semiconductor device including the substrate.

Semiconductor devices and substrates used in thereof

The invention provides a semiconductor package substrate, which includes a substrate, a chip contact area, an inner pad portion, an outer pad portion and a conductive layer. The chip contact area, the inner pad portion, the outer pad portion and the conductive layer are formed on one side of the substrate, wherein the outer pad portion encloses the inner pad portion that surrounds the chip contact area in the center of the substrate. The inner pad portion and the outer pad portion contain a plurality of signal pads and a plurality of shielding pads respectively, while the conductive layer and each of the shielding pads are electrically connected.

Substrate for semiconductor package

A substrate used in a semiconductor device. The substrate includes a first wiring layer, a second wiring layer, and an interconnection-wiring layer. The first wiring layer includes a plurality of first pads while the second wiring layer includes a plurality of second pads. The interconnection-wiring layer is set between the first and second wiring layer. In this case, at least one of the second pads isn't electrically connected with anyone of the first pads, and other second pads that located adjacent to this second pad, which is not electrically connected with the first pads, electrically connect to the interconnection-wiring layer. Furthermore, this invention also discloses a semiconductor device including the substrate.

Substrates for semiconductor devices with shielding for NC contacts

A method of arranging staggered bond pads layers for effectively reducing the size of a die. The sizes of different bond pad layers are reduced gradually from the upper layer to the lower layer, while the sizes of traces in different layers are increased from the upper layer to the lower layers. The size of the first layer is specified and determined by the specification of a wire bonder. The reduction of different bond pad layers may be linear or nonlinear.

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Hsinchu, Taiwan

Wei Feng Lin