Advanced Semiconductor Engineering, Inc.

Other

Institute for Information Industry

Wei-Chung Wang

Chian-Chi Lin

Min-Lung Huang

Ching-Huei Su

Po-Jen Cheng

Kuo-Chung Yee

Jian-Wen Lo

Chi-Chih Shen

Su Tao

Jen-Kuang Fang

Chun-Hung Lin

Yen-Ting Chen

Meng-Jen Wang

Kuo-Pin Yang

Jen-Chuan Chen

Cheng-Yin Lee

Chi-Wai Chow

Chia-Wei Chen

Hsueh-Te Wang

Sung-Mao Wu

Hsueh-An Yang

Hsiang-Chain Hsieh

Disclosed are a visible light communication system and a visible light communication method. In this system, a signal transmitter sends a visible light signal, and a signal light receiver capture an image of the visible light signal to recover the visible light signal according to the captured image. The signal receiver includes an image capturing module, an image processing module and a signal recovery module. The method includes: capturing an image of a visible light signal; processing the captured image of the visible light signal; determining whether there is a complete packet according to the processed image; if yes, directly recovering the visible light signal according to the processed image; but if no, executing a packet recovery process according to the processed image of the visible light signal, then obtaining the complete packet and recovering the visible light signal transmitted from the signal transmitter.

Visible light communication system and method

A package comprises a first unit including a semiconductor body, a hole, an isolation layer, a conductive layer and a solder. The semiconductor body has a first surface having a pad and a protection layer exposing the pad. The hole penetrates the semiconductor body. The isolation layer is disposed on the side wall of the hole. The conductive layer covers the pad, a part of the protection layer, and the isolation layer. The lower end of the conductive layer extends to below a second surface of the semiconductor body. The solder is disposed in the hole, and is electrically connected to the pad via the conductive layer. A second unit similar to the first unit and stacked thereon includes a lower end of a second conductive layer that extends to below a second surface of a second semiconductor body and contacts the upper end of the first solder.

Three-dimensional package and method of making the same

A circuit substrate suitable for being connected to at least one solder ball is provided. The circuit substrate includes a substrate, at least one bonding pad, and a solder mask. The substrate has a surface. The bonding pad is disposed on the surface of the substrate for being connected to the solder ball. The solder mask covers the surface of the substrate and has an opening for exposing a portion of the bonding pad. The opening has a first end and a second end. As compared with the second end, the first end is much farther from the bonding pad, and a diameter of the first end is larger than that of the second end.

Circuit substrate and method of fabricating the same and chip package structure

A stacked-type chip package structure including a first package structure, a second package structure, and a first molding compound is provided. The first package structure includes a first substrate, and a first chip stacked thereon and electrically connected thereto. The second package structure is stacked on the first package structure, and includes a second substrate, a second chip, and a plurality of solder blocks. The second chip is electrically connected to the second substrate, and the second substrate is electrically connected to the first substrate. The second chip is fixed on the first chip through an adhesive layer. The solder blocks are disposed on the back of the second substrate. The first molding compound is disposed on the first substrate and encapsulates the first package structure and the second package structure. The first molding compound has a recess for exposing the solder blocks.

Stacked-type chip package structure and method of fabricating the same

The invention relates to a microelectromechanical microphone packaging system. The microelectromechanical microphone packaging system comprises a substrate, a chip, a microelectromechanical microphone, a conductive glue, a non-conductive glue and a cover. The substrate has a first surface. The chip is mounted on the first surface of the substrate. The microelectromechanical microphone is mounted on the first surface of the substrate, and electrically connected to the chip. The chip is enclosed by the non-conductive glue. The non-conductive glue is enclosed by the conductive glue. The cover is mounted on the first surface of the substrate to form a containing space, and has an acoustic aperture. The microelectromechanical microphone packaging system utilizes the conductive glue enclosing the chip and the non-conductive glue to shield interference from outside noise and obtain a shielding effect. In addition, the cover does not need to be made of metal material.

Microelectromechanical microphone packaging system

A package and the method for making the same, and a stacked package, the method for making the package includes the following steps: (a) providing a carrier having a plurality of platforms; (b) providing a plurality of dice, and disposing the dice on the platforms; (c) performing a reflow process so that the dice are self-aligned on the platforms; (d) forming a molding compound in the gaps between the dice, and (e) performing a cutting process so as to form a plurality of packages. Since the dice are self-aligned on the platforms during the reflow process, a die attach machine with low accuracy can achieve highly accurate placement.

Package and the method for making the same, and a stacked package

A method of making a three-dimensional package, including: (a) providing a wafer; (b) forming at least one blind hole; (c) forming an isolation layer; (d) forming a conductive layer; (e) forming a dry film; (f) filling the blind hole with a solder; (g) removing the dry film; (h) patterning the conductive layer; (i) removing a part of the lower surface of the wafer and the isolation layer, so as to expose the conductive layer; (j) stacking a plurality of the wafers, and performing a reflow process; and (k) cutting the stacked wafers, so as to form a plurality of three-dimensional packages. As such, the lower end of the conductive layer is inserted into the solder of the lower wafer, so as to enhance the joint between the conductive layer and the solder, and effectively reduce the overall height of the three-dimensional packages after joining.

The present invention relates to a three-dimensional package and a method of making the same. The method comprises: (a) providing a semiconductor body; (b) forming at least one blind hole in the semiconductor body; (c) forming an isolation layer on the side wall of the blind hole; (d) forming a conductive layer on the isolation layer; (e) patterning the conductive layer; (f) removing a part of the lower surface of the semiconductor body and a part of the isolation layer, so as to expose a part of the conductive layer; (g) forming a solder on the lower end of the conductive layer; (h) stacking a plurality of the semiconductor bodies, and performing a reflow process; and (i) cutting the stacked semiconductor bodies, so as to form a plurality of three-dimensional packages. As such, the lower end of the conductive layer and the solder thereon are 'inserted' into the space formed by the conductive layer of the lower semiconductor body, so as to enhance the joining between the conductive layer and the solder, and effectively reduce the overall height of the three-dimensional packages after joining.

A three-dimensional package and a method of making the same including providing a wafer; forming at least one blind hole in the wafer; forming an isolation layer on the side wall of the blind hole; forming a conductive layer on the isolation layer; forming a dry film on the conductive layer; filling the blind hole with metal; removing the dry film, and patterning the conductive layer; removing a part of the metal in the blind hole to form a space; removing a part of the second surface of the wafer and a part of the isolation layer, to expose a part of the conductive layer; forming a solder on the lower end of the conductive layer, the melting point of the solder is lower than the metal; stacking a plurality of the wafers, and performing a reflow process; and cutting the stacked wafers, to form three-dimensional packages.

The present invention relates to a wafer level package and method for making the same. The method of the invention comprises: (a) providing a metal layer, the metal layer having a first surface and a second surface; (b) forming a plurality of first caves and a plurality of second caves on the first surface; (c) forming a cover in each first cave and around each first cave and forming a conductive portion in each second cave and around each second cave; (d) disposing a wafer onto the covers and the conductive portions; and (e) removing the metal layer. Whereby the process of the invention will be shortened and the cost will decrease. The method of invention provides the conductive portions used for convenient leads connecting with outer components and further decreases the size of the package.

Wafer level package and method for making the same

A three-dimensional package including a first wafer having at least one first pad and a first protection layer exposing the first pad. A first hole penetrates the first wafer. A first isolation layer is disposed on the side wall of the first hole. The lower end of a first conductive layer extends below the surface of the first wafer. A first metal is disposed in the first hole, and is electrically connected to the first pad via the first conductive layer. A first solder is disposed on the first metal in the first hole, wherein the melting point of the first solder is lower than that of the first metal. A second wafer is configured similarly as the first wafer. A lower end of a second conductive layer of the second wafer extends below the surface of the second wafer and contacts the upper end of the first solder.

A method of fabricating protective caps for protecting devices on wafer surface includes: (a) providing a non-metal cap substrate and forming a metal layer on the non-metal cap substrate; (b) forming a plurality of cavities on a surface of the metal layer, wherein the location of each cavity corresponds to each of the devices on the wafer surface; and (c) forming a protective cap in each cavity and forming a plurality of bonding media around the cavities.

Method for fabricating protective caps for protecting elements on a wafer surface

A method and apparatus for molding a flip chip semiconductor device are disclosed herein. A substrate having at least one air hole is provided. A chip is mounted on the substrate by multiple solder balls such that the air hole is beneath the chip and surrounded by the multiple solder balls. The substrate mounted with the chip is placed in a mold apparatus which defines at least one air channel aligning with the air hole, such that air can be exhausted via the air hole and the air channel when encapsulation material is filling the mold apparatus.

Method and apparatus for molding a flip chip semiconductor device

A packaging process providing a die with C4 solder bumps and a polymer substrate first. It then jets the melted second solder onto each of the C4 solder bumps forming a second solder bump. After reflowing and leveling the solder bumps, the die is flipped and combined with the substrate. Then heat treatment proceeds with the combination of the die and the substrate forming a flip chip package with collapse-controlled solder bump on the polymer substrate.

Method and structure for forming flip chip with collapse-controlled solder bumps on a substrate

A flip-chip semiconductor device and a method for under filling the flip-chip semiconductor device are disclosed. The flip-chip semiconductor device is provided with a substrate and a die having a plurality of solder bumps for connecting to the substrate. Encapsulation material is under filled between the die and the substrate. The substrate has a non-mask area defied in a center portion thereof while the remaining surface area is covered by a solder mask. The non-mask area defines a hole in the center thereof so that the encapsulation material can be dispensed along all sides of the die to flow toward the non-mask area and stop when reaching the non-mask area whereby the encapsulation material does not block the hole and air between said die and the substrate is limited in a void formed around the hole and communicated with the atmosphere via the hole.

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Kaohsiung, Taiwan

Wei-Chung Wang