United Microelectronics Corp.

Wei-Chung Chen

C C Hsue

Ching-Chun Hwang

Meng-Jin Tsai

Chien-Kuo Yang

Fei-Hung Chen

A method of forming a local interconnect is provided. A semiconductor is provided. An isolation structure, a transistor and a conductive layer are formed on the substrate. A dielectric layer with an opening is formed over the substrate. A part of the dielectric layer is removed by a photolithography and etching process to form a via opening to expose a part of the gate of the transistor or a part of the conductive layer. A conformal barrier layer is formed in the via opening and overflows the dielectric layer. A conductive plug is formed in the via opening. The barrier layer is patterned to form a local interconnect.

Method of fabricating local interconnect

A method for forming enhanced field oxide (FOX) region of low voltage devices in a high voltage process is disclosed. The method includes providing a semiconductor structure comprising a substrate, two field oxide regions on the substrate, a well between the two field oxide regions in the substrate and a silicon nitride layer between the two field oxide regions above the well. As a key step, nitrogen is implanted into the semiconductor structure, and the silicon nitride layer is then removed. Then, a gate oxide layer on the well and silicon oxynitride layer on the field oxide regions are all formed in-situ.

Method for forming enhanced FOX region of low voltage device in high voltage process

A method of fabricating a capacitor on a semiconductor substrate. A barrier layer is formed over the substrate to serve as a bottom electrode of the capacitor. A dielectric layer is formed on the barrier layer. An upper electrode is formed on the dielectric layer. In addition, the method can be used in a dynamic random access memory.

Method of fabricating capacitor

A method for producing self-aligned silicidation, substantially facilitating the integration of the high-voltage and low-voltage MOS device, is disclosed. The method includes providing, the present invention provides a integration of high-voltage and low-voltage MOS transistor, which self-aligned silicidation process. A substrate is provided incorporating a device, wherein the device is defined high-voltage MOS region and low-voltage MOS region. Sequentially, a plurality of field oxides are formed on the substrate, one of the field oxide is spaced from another of the field oxide by a MOS region. Moreover, a polysilicon layer is formed over said high-voltage MOS region and low-voltage MOS region, and a first dielectric layer is deposited above the polysilicon layer of the high-voltage MOS region and low-voltage MOS region. Consequently, a first photoresist layer is formed over the first dielectric layer, wherein defining and etching the first photoresist layer to form gates of high-voltage MOS and low-voltage MOS. Then, using said second photoresist layer as a mask above low-voltage MOS region, firstly implanting the substrate of the high-voltage MOS region to form conductivity-type grade therein, and then the second photoresist layer of low-voltage MOS region is removed. Moreover, spacers are formed on sidewall of said gates of high-voltage MOS and low-voltage MOS, and then a second dielectric layer is formed on the substrate of high-voltage and low-voltage MOS.

Growing community of inventors

Hsin-Chu, Taiwan

Wei-Chung Chen