Taiwan Semiconductor Manufacturing Comp. Ltd.

Wei-Chih Weng

Hsun-Ying Huang

Dun-Nian Yaung

Jen-Cheng Liu

Jeng-Shyan Lin

Yu-Yang Shen

Yung-Cheng Chang

Jin-Hong Cho

Chien Nan Tu

Chun-Wei Chia

Hsien-Liang Meng

Chun-Liang Lu

Chih-Ho Tai

Bo-Chang Su

Kuo-cheng Lee

Tse Yu Tu

Chun-hao Chou

A CMOS image sensor includes a unit pixel array including a photodiode array, a color filter array, a micro-lens array, and a grid isolation structure laterally separating adjacent color filters. The grid isolation structure includes a first low-n grid, a second low-n grid underlying the first low-n grid, and a metal grid within the second low-n grid, the first low-n grid being narrower than the second low-n grid. The color filter array includes color filter matrixes, all color filter matrixes have the same arrangement pattern. Sizes of color filters in each color filter matrix vary depending on locations of the color filters in the color filter matrix. In an edge portion, a distance between a center of a color filter matrix and a center of a corresponding unit pixel matrix in plan view varies depending on a location of the unit pixel matrix in the CMOS image sensor.

CMOS image sensor and method for making the same

The present disclosure, in some embodiments, relates to a method of forming an integrated chip structure. The method includes forming a first dielectric bonding layer over a first dielectric structure, which is disposed on a first substrate and surrounds a first plurality of interconnects. The first dielectric bonding layer is patterned to form a first recess exposing one of the first plurality of interconnects. A first conductive bonding segment is formed within the first recess. A second dielectric bonding layer is formed over a TSV extending through a second substrate. The second dielectric bonding layer is patterned to form a second recess exposing the TSV. A second conductive bonding segment is formed within the second recess. The first substrate is bonded to the second substrate along an interface comprising dielectric and conductive regions. The conductive region includes a conductive interface between the first and second conductive bonding segments.

Stacked substrate structure with inter-tier interconnection

The present disclosure, in some embodiments, relates to an integrated chip structure. The integrated chip structure includes a first plurality of interconnects within a first dielectric structure on a first substrate, and a second plurality of interconnects within a second dielectric structure on a second substrate. A bonding structure is arranged between the first dielectric structure and the second substrate. An inter-tier interconnect structure extends between the first plurality of interconnects and the second plurality of interconnects and through the second substrate. The inter-tier interconnect structure includes a first region having substantially vertical sidewalls extending through the second substrate and a second region surrounded by the bonding structure. The second region contacts a bottom of the first region and has tapered sidewalls.

The present disclosure, in some embodiments, relates to a multi-dimensional integrated chip structure. The structure includes a first interconnect layer within a first dielectric structure on a first substrate, and a second interconnect layer within a second dielectric structure on a second substrate. A bonding structure is between the first dielectric structure and the second substrate. An inter-tier interconnect structure extends through the second substrate and between a top of the first interconnect layer and a bottom of the second interconnect layer. The inter-tier interconnect structure includes a first region having substantially vertical sidewalls extending through the second substrate and a second region below the first region and having tapered sidewalls surrounded by the bonding structure.

The present disclosure relates to a method of forming a multi-dimensional integrated chip having tiers connected in a front-to-back configuration, and an associated apparatus. In some embodiments, the method is performed by forming one or more semiconductor devices within a first substrate, forming one or more image sensing elements within a second substrate, and bonding a first dielectric structure over the first substrate to a back-side of the second substrate by way of a bonding structure. An inter-tier interconnect structure, comprising a plurality of different segments, respectively having sidewalls with different sidewall angles, is formed to extend through the bonding structure and the second substrate. The inter-tier interconnect structure is configured to electrically couple a first metal interconnect layer over the first substrate to a second metal interconnect layer over the second substrate.

Embodiments of mechanisms of a backside illuminated image sensor device structure are provided. The backside illuminated image sensor device structure includes a substrate having a frontside and a backside and a pixel array formed in the frontside of the substrate. The backside illuminated image sensor device structure further includes an antireflective layer formed over the backside of the substrate, and the antireflective layer is made of silicon carbide nitride.

Mechanisms for forming backside illuminated image sensor device structure

Provided is a semiconductor image sensor device. The image sensor device includes a semiconductor substrate that includes an array region and a black level correction region. The array region contains a plurality of radiation-sensitive pixels. The black level correction region contains one or more reference pixels. The substrate has a front side and a back side. The image sensor device includes a first compressively-stressed layer formed on the back side of the substrate. The first compressively-stressed layer contains silicon nitride. The image sensor device includes a metal shield formed on the compressively-stressed layer. The metal shield is formed over at least a portion of the black level correction region. The image sensor device includes a second compressively-stressed layer formed on the metal shield and the first compressively-stressed layer. The second compressively-stressed layer contains silicon oxide. A sidewall of the metal shield is protected by the second compressively-stressed layer.

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Tainan, Taiwan

Wei-Chih Weng