Via Technologies, Inc.

Wistron Corporation

Wei-Chih Lai

Wen-Yuan Chang

Yeh-Chi Hsu

Ying-Ni Lee

Wei-Chiao Huang

Yung-Yu Huang

Yu-Kai Chen

Li-Cheng Yeh

Jiang Fan

A chip package structure includes a carrier and a chip group. The chip group includes a pair of first chips that are identical IC chips. The pair of first chips are disposed on the carrier in opposite directions and parallel to each other, and electrically connected with the carrier.

Chip package structure

A power control device for an electronic device includes a power switching unit for switching to output a dc power source to a load of the electronic device according to a power switching signal, a switching detection unit for responding a power switching status to generate a switching detection signal, a status latch module for generating the power switching signal according to the switching detection signal, a first status signal and a second status signal, and a logic unit for generating the first status signal and the second status signal for the status latch module according to the power switching signal, such that the status latch module latches the first status signal and the second status signal.

Power control device using status latch module and electronic device using the same

An integrated circuit (IC) package includes an IC chip, a package carrier, and a plurality of conductive bumps connecting the IC chip to the package carrier. The IC chip includes a substrate and an IC layered structure configured on an active surface of the substrate. The active surface has a core area and a signal area surrounding the core area. The IC layered structure includes a first physical layer interface. The first physical layer interface includes a plurality of first bump pads and a plurality of first inner pads electrically connected to the first bump pads, respectively. The first inner pads are arranged in multiple rows in the signal area.

Integrated circuit package and physical layer interface arrangement

An integrated circuit (IC) package includes an IC chip and a package carrier. The IC chip includes a substrate and an IC layered structure configured on an active surface of the substrate. The IC layered structure includes a first physical layer interface and a second physical layer interface. The first physical layer interface includes a plurality of first bump pads and a plurality of first inner pads electrically connected to the first bump pads, respectively. The second physical layer interface includes a plurality of second bump pads and a plurality of second inner pads electrically connected to the second bump pads, respectively. The second bump pads are mirror images of the first bump pads with respect to a first geometric plane perpendicular to the active surface. The second inner pads are mirror images of the first inner pads with respect to the first geometric plane.

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Taipei, Taiwan

Wei-Chih Lai