Taiwan Semiconductor Manufacturing Comp. Ltd.

Other

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Wei-Chih Chen

Yu-Hsiang Hu

Hung-Jui Kuo

Sih-Hao Liao

Hung-Chun Cho

Chung-Hui Chen

Po-Han Wang

Jeng-Hong Chen

Kuang-Hu Huang

Hao-Chieh Chan

Jen-Ti Wang

Chih-Wei Sung

Wei-Chung Peng

Jing-Syuan Jia

I-Ken Ho

Pete Hsinhsiang Liu

De-Hao Tseng

Shou-Te Wei

Chen-Hua Douglas Yu

Chung-Shi Liu

Yung-Chi Chu

Kuo-Fong Chuang

Tsung-Ding Wang

Chii-Ping Chen

Hao-Cheng Hou

Wen-Sheh Huang

Jung-Wei Cheng

Wan-Te Chen

Sheng-Feng Liu

Bi-Ling Lin

Meng-Che Tu

Chien-Hsun Lee

Wen-Ming Chen

Ting-Wei Wang

Cheng-Ho Hung

Shi-Chi Chen

Jun-Hao Wu

Chi-Yuan Chu

Hao-Yi Tsai

Ming Hung Tseng

Hsin-Yu Pan

Tsung-Hsien Chiang

Tzu-Sung Huang

Chien-Hsun Chen

Ming-Tan Lee

Chao-Hsien Huang

Ban-Li Wu

Chun-Jung Huang

Zhengxiang Wang

Yung-Lin Hsu

Yi-Che Chiang

Chih-Hao Chang

Wei-Kang Hsieh

Kuang-Huan Hsu

Ting-Chen Tseng

Tuan-Yu Hung

Yuh-Sen Chang

Ping-Fu Wang

Yung-Chih Liu

Chih-Yuan Chiu

Chih-Hung Liu

Yi-Ting Hu

Min-Yu Wu

Tung-Hsiao Yu

Pin-Yi Shin

Yu-Lin Wang

Pei-Shan Wu

Yung-Chuan Chen

Gui Feng Zhou

Yao-Chuan Hu

A package structure and a method of forming the same are provided. The package structure includes a first die, a second die, a first encapsulant, and a buffer layer. The first die and the second die are disposed side by side. The first encapsulant encapsulates the first die and the second die. The second die includes a die stack encapsulated by a second encapsulant encapsulating a die stack. The buffer layer is disposed between the first encapsulant and the second encapsulant and covers at least a sidewall of the second die and disposed between the first encapsulant and the second encapsulant. The buffer layer has a Young's modulus less than a Young's modulus of the first encapsulant and a Young's modulus of the second encapsulant.

Package structure comprising buffer layer for reducing thermal stress and method of forming the same

A method of manufacturing a semiconductor package includes depositing a first dielectric layer over a carrier substrate. A first metallization pattern is formed over the first dielectric layer. The first metallization pattern has a first opening exposing the first dielectric layer. A second dielectric layer is deposited over the first metallization pattern, forming a dielectric slot through the first metallization pattern by filling the first opening. A second metallization pattern and a third dielectric layer are formed over the second dielectric layer. A through via is formed over the third dielectric layer, so that the dielectric slot is laterally under the through via.

Dielectric slots underneath conductive vias in interconnect structure of semiconductor package and method of forming the same

A passivation layer and conductive via are provided, wherein the transmittance of an imaging energy is increased within the material of the passivation layer. The increase in transmittance allows for a greater cross-linking that helps to increase control over the contours of openings formed within the passivation layer. Once the openings are formed, the conductive vias can be formed within the openings.

Methods of manufacture having redistribution layer using dielectric material photoactive component

A package structure includes a first redistribution layer, a semiconductor die and a second redistribution layer. The first redistribution layer includes a first dielectric layer, first conductive elements, second conductive elements, a top dielectric layer and an auxiliary dielectric portion. The first conductive elements and the second conductive elements are disposed on the first dielectric layer with a first pattern density and a second pattern density respectively. The top dielectric layer is disposed on the first dielectric layer and covering a top surface of the second conductive elements. The auxiliary dielectric portion is disposed in between the first dielectric layer and the top dielectric layer, and covering a top surface of the first conductive elements. The semiconductor die is disposed on the first redistribution layer. The second redistribution layer is disposed on the semiconductor die, and electrically connected to the semiconductor die and the first redistribution layer.

Package structure including auxiliary dielectric portion

A semiconductor package includes a semiconductor die and a redistribution structure. The semiconductor die is laterally surrounded by a molding compound, and the semiconductor die has a conductive pillar and a complex compound sheath sandwiched between the conductive pillar and the molding compound. The redistribution structure is electrically connected with the semiconductor die and comprises a first via portion at a first side of the redistribution structure and a second via portion at a second side of the redistribution structure, and a base angle of the second via portion is greater than a base angle of the first via portion.

Semiconductor package and method of forming the same

A package structure includes a semiconductor die and a first redistribution circuit structure. The first redistribution circuit structure is disposed on and electrically connected to the semiconductor die, and includes a first build-up layer. The first build-up layer includes a first metallization layer and a first dielectric layer laterally wrapping the first metallization layer, wherein at least a portion of the first metallization layer is protruded out of the first dielectric layer.

Package structure and method of manufacturing the same

A method of forming a semiconductor device includes forming a first dielectric layer over a front side of a wafer, the wafer having a plurality of dies at the front side of the wafer, the first dielectric layer having a first shrinkage ratio smaller than a first pre-determined threshold; curing the first dielectric layer at a first temperature, where after curing the first dielectric layer, a first distance between a highest point of an upper surface of the first dielectric layer and a lowest point of the upper surface of the first dielectric layer is smaller than a second pre-determined threshold; thinning the wafer from a backside of the wafer; and performing a dicing process to separate the plurality of dies into individual dies.

Semiconductor package and methods of forming the same

A redistribution structure is made using filler-free insulating materials with a high shrinkage rate. As a result, good planarity may be achieved without the need to perform a planarization of each insulating layer of the redistribution structure, thereby simplifying the formation of the redistribution structure.

Integrated fan out device with a filler-free insulating material

Methods of manufacture of semiconductor devices having redistribution layer using dielectric material having photoactive component

A method includes moving a wafer transport device to a position above a load port; lowering a hoist unit of the wafer transport device above the load port, wherein the wafer transport device has a plurality of belts, each of the belts is connected to the hoist unit and wound around a respective belt winding drum; detecting sound waves from the belts by using at least one acoustic sensor to measure tensions of the belts; and comparing the tensions from the belts to determine an inclination of the hoist unit.

Method for transporting wafers

A die includes a substrate, a conductive pad, a connector and a protection layer. The conductive pad is disposed over the substrate. The connector is disposed on the conductive pad. The connector includes a seed layer and a conductive post. The protection layer laterally covers the connector. Topmost surfaces of the seed layer and the conductive post and a top surface of the protection layer are level with each other.

Die and package structure

A package structure and method of forming the same are provided. The package structure includes a polymer layer, a redistribution layer, a die, and an adhesion promoter layer. The redistribution layer is disposed over the polymer layer. The die is sandwiched between the polymer layer and the redistribution layer. The adhesion promoter layer, an oxide layer, a through via, and an encapsulant are sandwiched between the polymer layer and the redistribution layer. The encapsulant is laterally encapsulates the die. The through via extends through the encapsulant. The adhesion promoter layer and the oxide layer are laterally sandwiched between the through via and the encapsulant. A bottom portion of the encapsulant is longitudinally sandwiched between the adhesion promoter layer and the polymer layer.

Package structure and method of forming the same

A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a resistive element over the substrate. The semiconductor device structure also includes a thermal conductive element over the substrate. A direct projection of the thermal conductive element on a main surface of the resistive element extends across a portion of a first imaginary line and a portion of a second imaginary line of the main surface. The first imaginary line is perpendicular to the second imaginary line, and the first imaginary line and the second imaginary line intersect at a center of the main surface.

Semiconductor device structure with resistive element

A thermally insulating fixture includes a self-tapping screw, a fixed member mounted on the self-tapping screw, and a thermally insulating member wrapping the fixed member. The fixed member is provided with a first through hole. The thermally insulating member is provided with a second through hole and a positioning groove. The self-tapping screw extends through the second through hole of the thermally insulating member and the first through hole of the fixed member. A thermally insulating cover is mounted in the positioning groove and covers the self-tapping screw. The thermally insulating cover has a receiving space which receives the self-tapping screw. The thermally insulating cover has a positioning flange which is positioned in the positioning groove when the thermally insulating cover covers the head of the self-tapping screw.

Thermally insulating fixture

Growing community of inventors

Taipei, Taiwan

Wei-Chih Chen