Hon Hai Precision Industry Co., Ltd.

Via Technologies, Inc.

Industrial Technology Research Institute

Via Alliance Semiconductor Co., Ltd.

Synopsys, Inc.

Chicony Electronics Co., Ltd.

Shanghai Zhaoxin Semiconductor Co., Ltd.

Asia Vital Components Co., Ltd.

Industrial Technical Research Institute

Taiwan Cement Corporation

Wei-Cheng Chen

Wen-Yuan Chang

Chen-Yueh Kung

Yeh-Chi Hsu

Hsueh-Chung Shelton Lu

Shiang-Ruei Ouyang

Der-Ray Huang

Guo-Zua Wu

Zu-Wen Chao

Chien-Chang Wang

Robert Cameron Doig

Jen-Feng Huang

Chin-Ming Huang

Shoung Ouyang

Heng-Wen Hsu

Chia-Lin Liu

Chu-Hsien Chou

Shih-Chieh Lin

Chien-Sheng Liu

Yu-Hsiu Chang

Chau-Shin Jang

Jin-Kae Jang

Hung-Yun Huang

Cheng-Hsien Shen

Chun-Min Chen

Hideo Sato

Yao-Jih Hung

Hao-Ting Tien

Tsung-You Wang

I-Wei Chen

Pi-cheng Tung

Ren-bin Xiao

Mitsuru Goto

Yung Le Wang

Chun-Jung Shih

Wan-Hsia Liu

Vincent Hsu

Ping-Chi Kuo

A camera module includes a circuit board, an image sensor, a filter removable switch, a camera lens, and a thermally conductive structure. The circuit board has a surface. The image sensor is disposed on the surface. The filter removable switch is located over the surface. The camera lens is on the light-sensing path of the image sensor. The thermally conductive structure is contacted between the circuit board and the filter removable switch and has a channel. The image sensor is located in the channel.

Camera module

An array substrate carrying a display area and a camera area surrounded by the display area provides connections to both areas free of electrical interference. The camera area includes a transparent area and a routing area surrounding the transparent area. The array substrate includes a first conductive layer and a second conductive layer. The first conductive layer includes first wires and first capacitance compensation patterns. The second conductive layer includes second wires. Each first capacitance compensation pattern is between adjacent first wires. Along a thickness direction of the array substrate, a projection of each first capacitance compensation pattern on the substrate overlaps with a projection of at least one second wire. A display panel and a display device are also disclosed.

Array substrate for reducing parasitic capacitance between adjacent wires, display panel, and display device

A chip package array including a plurality of chip packages is provided. The chip packages are suitable for array arrangement to form the chip package array. Each of the chip packages includes a redistribution structure, a supporting structure, a chip, and an encapsulated material. The supporting structure is disposed on the redistribution structure and has an opening. The chip is disposed on the redistribution structure and located in the opening. The encapsulated material is located between the opening and the chip, wherein the encapsulated material is filled between the opening and the chip, and the chip and the supporting structure are respectively connected to the redistribution structure.

Chip package array, and chip package

A gate scanning unit circuit is applied in a display panel including a number of gate lines and a driver configured to output clock signals. The gate scanning unit circuit is configured to scan the number of gate lines. The gate scanning unit circuit includes a flip-flop and at least two output units. The flip-flop is configured to output a trigger signal. Each output unit is connected to the flip-flop and the driver. Each of the at least two output units is connected to the number of gate lines one-to-one. The output unit is configured to output a gate scan signal to the corresponding connected gate line according to the trigger signal and the clock signals.

Display panel, gate scanning circuit, and gate scanning unit circuit

A chip package process includes the following steps. A supporting structure and a carrier plate are provided. The supporting structure has a plurality of openings. The supporting structure is disposed on the carrier plate. A plurality of chips is disposed on the carrier plate. The chips are respectively located in the openings of the supporting structure. An encapsulated material is formed to cover the supporting structure and the chips. The supporting structure and the chips are located between the encapsulated material and the carrier plate. The encapsulated material is filled between the openings and the chips. The carrier plate is removed. A redistribution structure is disposed on the supporting structure, wherein the redistribution structure is connected to the chips.

Chip package process

A display area for displaying images and a camera area surrounded by the display area are both founded on an array substrate. The camera area defines a transparent area and a wire-routing area surrounding the transparent area. The array substrate includes first data lines, second data lines, and first scan lines. Each first data line, each second data line, and each first scan line avoid the transparent area and cross the wire-routing area. Each second data line includes an auxiliary data line and a data line lead. The first scan lines and the auxiliary data lines are defined by a first conductive layer, the first data lines and the data line leads are defined in a second conductive layer insulated and spaced from the first conductive layer, such a stacked arrangement allows an optically-clear path for the camera to collect light.

Array substrate, display panel and display device

A device with a display uninterrupted by a camera includes a display panel and the camera. The display device defines a display area for displaying images and a light transmission area surrounded by the display area. The camera is in the light transmission area and can collect light for images through the light transmission area.

Display device

A chip packaging method includes followings steps. A plurality of first chips are disposed on a carrier, wherein each of the first chips has a first active surface, and a plurality of first conductive pillars are disposed on the first active surface. A second active surface of a second chip is electrically connected to the first active surfaces of the first chips through a plurality of second conductive pillars. An encapsulated material is formed, wherein the encapsulated material covers the plurality of first chips, the plurality of first conductive pillars, the second chip and the plurality of second conductive pillars. The encapsulated material is partially removed to expose each of the plurality of first conductive pillars. A redistribution structure is formed on the encapsulated material, wherein the redistribution structure connects with the first conductive pillars.

Chip packaging method

A multi-layered circuit board structure includes a first circuit board, a second circuit board, and a heat dissipation plate. The first circuit board includes a first surface. The second circuit board includes a second surface facing the first surface. The heat dissipation plate is located between the first circuit board and the second circuit board. The heat dissipation plate includes a substrate and a fixing base integrally extending from the substrate and bent. The fixing base includes a connecting plate, a first plate, and a second plate spaced apart from the first plate. The connecting plate is connected between the first plate and the second plate. The first surface is bonded to a surface of the first plate, the second surface is bonded to a surface of the second plate, and the substrate is in contact with neither the first surface nor the second surface.

Multi-layer circuit board structure

A chip package structure includes a plurality of first chips, a plurality of first conductive pillars, a second chip, a plurality of second conductive pillars, an encapsulated material and a redistribution structure. Each first chip has a first active surface. Each of the first conductive pillars is disposed on the first active surface of the corresponding first chip. A second active surface of the second chip is electrically connected to the first active surfaces of the first chips through the second conductive pillars. The encapsulated material partially covers the first chips, the first conductive pillars, the second chip and the second conductive pillars. The redistribution structure is disposed on the encapsulated material and connects the first conductive pillars. A chip package structure array is also provided.

Chip package structure and chip package structure array

A probe card including a circuit board, a transformer, a probe head, and a reinforcement structure is provided. The transformer including a body, a plurality of solder balls, and a plurality of first contact points are disposed on the substrate. The body has a first surface and a second surface, wherein the first surface is located between the circuit board and the second surface. The solder balls are disposed on the first surface, and the first contact points are disposed on the second surface. The probe head is disposed on the second surface. The probe head is electrically connected to the circuit board by the first solder balls. The reinforcement structure is disposed between the probe head and the circuit board.

Probe card

A computer-implemented method is disclosed for speeding up database access of electronic design automation (EDA) tool which utilizes a database manager for file access. The EDA tool accesses a plurality of design files, and each of the plurality of design files is associated with one of a plurality of design units for an integrated circuit (IC). The plurality of design files are encapsulated into an archive file which comprises a plurality of data units, wherein each of the data units corresponds to a design file. A request to access a design file will be redirected to access the archive file. The design file is then accessed by accessing the corresponding data unit in the archive file.

Method of speeding up access to design databases having large numbers of design units

An electronic structure is provided with a redistribution structure and the following elements. A first supporting structure has a first opening and is disposed on a first surface of the redistribution structure. A second supporting structure has a second opening and is disposed on a second surface of the redistribution structure opposite to the first surface. A first bonding protruding portions are disposed on the first surface of the redistribution structure and located in the first opening. A second bonding protruding portions are disposed on the second surface of the redistribution structure and located in the second opening. A first encapsulated material is filled between the first opening and the first bonding protruding portions. A second encapsulated material is filled between the second opening and the second bonding protruding portions. An electronic structure array is also provided.

Electronic structure, and electronic structure array

Growing community of inventors

Taipei, Taiwan

Wei-Cheng Chen