Lsi Logic Corporation

Wee Keong Liew

Aritharan Thurairajaratnam

Chok J Chia

Seng Sooi Lim

Hong Tee Lim

Chengyu Guo

Nadeem Haque

Maniam B Alagaratnam

A BGA package having a multiplicity of power segments configured for power connection to integrated circuit die is disclosed. The BGA package substrate includes an integrated circuit die and a ground ring. The substrate also includes a first power ring with a plurality of spaced apart first power ring segments arranged around the die. A second power ring having a plurality of spaced apart conductive second ring segments is also formed around the die. A plurality of vias that penetrate through the substrate are provided to accommodate electrical connections to the segments of the first and second power rings and to the ground ring. The package includes bonding wires for connecting the die to the first and second ring segments and ground ring. Additionally, the package is commonly encapsulated to protect the die and wires. In some implementations, the conductive first ring segments are arranged in staggered configuration relative to the conductive second ring segments with each of the first ring segments having a conductive tab configured so that it passes through spaces between the conductive second ring segments. The tabs electrically connecting the first ring segments to vias.

Integrated circuit package and method for a PBGA package having a multiplicity of staggered power ring segments for power connection to integrated circuit die

A method for fabricating a semiconductor package having a 2-layer substrate, which includes an array of solder balls, is disclosed. The method includes patterning signal traces on a top layer of the substrate and identifying groups of signal traces to isolate. According to the present invention, a grounded isolation trace is then patterned adjacent to one of the groups of traces to isolate the signal traces, thereby providing noise shielding. In a preferred embodiment, the grounded isolation trace is provided with multiple vias, rather than only one. In a further aspect of the present invention a row of solder balls is connected together and to ground to create a bottom-layer isolating ground trace to further reduce noise. The bottom-layer isolating ground trace may be connected to the top-layer isolating ground trace using a via.

PBGA electrical noise isolation of signal traces

A two layer PBGA which includes a metal ground plane at its bottom layer. The ground plane is preferably a metal plane which is connected to ground through a metal connection to a ball pad at the center of the package and a ball pad proximate the edge of the package. The ground plane is voided around the signal and power balls, via and &ldquo;dog bones&rdquo;. The PBGA is configured such that the ground plane serves effectively the same function as the second layer ground plane in a conventional four layer PBGA. The PBGA provides a cheaper alternative to the generally more expensive four layer PBGA, and provides better cross talk performance (especially for high frequency signaling) as well as better thermal performance as a result of having more metal at the bottom layer of the package.

Ground plane on 2 layer PBGA

An integrated circuit package is provided that allows high density routing of signal lines. A substrate of the package may include an upper surface upon which a bonding finger resides, a lower surface upon which a solder ball resides, and a signal conductor plane on which a signal trace conductor resides a dielectrically spaced distance between the upper surface and the lower surface. A first via may extend perpendicularly from the upper surface, connecting the bonding finger to the first portion of the signal trace conductor. A second via may extend perpendicularly from the lower surface, connecting the solder ball to the second portion of the signal trace conductor. The routing of the vias and signal trace conductors may cause the signal lines to either fan into or away from the area of the integrated circuit package adapted to receive the integrated circuit.

Integrated circuit package substrate with high density routing mechanism

A mold for use in encapsulating an integrated circuit, wherein an encapsulant is injected into the mold during packaging of the integrated circuit. The improvement to the mold is a shaped member having an abutting surface for contacting a surface of the integrated circuit and thereby substantially preventing encapsulant from adhering to the surface of the integrated circuit, whereby the surface of the integrated circuit is left exposed. Because the surface of the integrated circuit is left exposed, the encapsulant used to encapsulate the integrated circuit does not form a thermal barrier between the integrated circuit and the exterior of the package. Thus, the packaged integrated circuit is able to more efficiently conduct heat away from the integrated circuit.

Molded integrated circuit package

A method and apparatus for providing a ball grid array assembly formed from interlocking ball grid array packages is disclosed. Each of the ball grid array packages has interlocking edge features for mechanical connection, whereby joining the plurality of ball grid array packages via the interlocking edge features forms the interlocking ball grid array assembly. The interlocking ball grid array assembly may then be mounted on a PC board as a single unit.

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San Jose, CA, United States of America

Wee Keong Liew