Union Semiconductor Technology Corporation

Other

Union Semiconductor Technology Center

Wayne Theel

An apparatus for improving stability of a magnetoresistive random access memory over process and operational variations includes a current reference circuit that provides a reference current control signal to variable analog control circuitry. The variable analog control circuitry is connected to receive control signals from the current reference. The variable analog control circuitry generates a word current reference signal in response to the reference current control signal and further generates a source current reference signal in response to the reference current control signal. At least one word current source is connected to receive the word current reference signal. At least one sense current source is connected to receive the source current reference signal.

Apparatus to improve stability of an MRAM over process and operational variations

A method to adjust an operating parameter of a magnetoresistive random access memory having a tunable circuit, such as a bias control circuit, provides for measuring the operating parameter, such as a word current or sense current, of the magnetoresistive random access memory to obtain a measured operating parameter result and tuning the tunable circuit, such as with trimmable resistors, based on the measured operating parameter result. A method is also provided to adjust an operating parameter of a wafer of magnetic random access memories each having a tunable circuit by measuring the operating parameter one or more of the magnetic random access memories to obtain a measured operating parameter result and tuning some or all of the tunable circuits based on the measured operating parameter result.

Method for optimizing MRAM circuit performance

A magnetic random access memory () with equalization has a plurality of magnetic memory elements that perform a memory operation. A word line magnetically activates at least one magnetic memory element. A sense line detects the state of the at least one magnetic memory element. A word line driver is connected to the word line to drive a current on the word line during the memory operation. A word line equalizer is connected to the word line to equalize the word line during the non-memory operations.

Method to equalize word current circuitry

A word current source () for a magnetoresistive random access memory circuit () includes an n-channel transistor () including a gate, a source and a drain, where the source is coupled to a supply ground, and the drain is coupled to the magnetoresistive random access memory circuit. A positive supply voltage is coupled to the magnetoresistive random access memory circuit () so as to allow current to flow through the magnetoresistive random access memory circuit () when an activation signal is applied to the gate by the control circuit.

Optimized MRAM current sources

A current controlled sense current source having a current source with a stable reference current output is provided with a sense current source having a sense current reference input connected to the stable reference current output with the sense current source having a sense current output. A current controlled word current source comprising a current source having a stable reference current output is also provided with a word current source having a word current reference input connected to the stable reference current output with the word current source having a word current output.

Current controlled word and sense source

A semiconductor device includes a primary memory array, primary addressing circuitry, a redundant memory array, redundant addressing circuitry, and a first signal pad. The primary memory array includes primary memory elements operable to store data, and the primary addressing circuit is operable to select the primary memory elements. The redundant memory array includes redundant memory elements operable to store data and is also operable to be programmed from a programmable state to provide redundant memory elements for defective primary memory elements. The first signal pad is operable to receive serial selection data, and the redundant addressing circuit is connected to the first signal pad and is operable to receive the serial selection data from the first signal pad and select the redundant memory elements in response.

Apparatus and method for testing redundant memory elements

A semiconductor device includes a first power pad, a second power pad, a first adjacent bus pair, and a second adjacent bus pair. The first power pad is operable to supply a first potential, and the second power pad operable to supply a second potential. The first adjacent bus pair is disposed on a first layer of the semiconductor device and connected to the first and second power pad. The second adjacent bus pair is disposed on the second layer of the semiconductor device and is connected to the first and second power pads, and is also underlying the first adjacent bus pair.

Interlayered power bus for semiconductor device

A semiconductor device a first power pad, a second power pad, a first power network, and a second power network. The first power pad is operable to supply a first potential, and the second power pad is operable to supply a second potential. The first power network defines a first periphery in the semiconductor device and is coupled to the first power pad and the second power pad. The second power network defines a second periphery in the semiconductor device and is coupled to the first power pad and the second power pad.

Semiconductor device power bus system and method

MRAM sensing operations use a word line () and a sense current to detect the state of a bit (). The bit () has a high resistance or a low resistance state. Using multiple sub bits () in each bit () increases the difference between the high resistance and low resistance state in proportion to the number of sub bits () in each bit (). Multiple sub bits () also provide redundancy in the event of failure of a sub bit (). The MRAM can be designed to function with one or more sub bits () being defective.

MRAM signal size increasing apparatus and methods

A magnetoresistive random access memory (MRAM) device includes a memory array having a plurality of bitlines and a plurality of wordlines intersecting the bitlines. A plurality of memory elements are located at the intersections of the wordlines and the bitlines and are operable to store data. A bitline selection circuit is operable to select a first bitline and to provide a first sense current to the first bitline to generate a first reference signal. A wordline selection circuit is operable to select wordlines and to provide wordline currents to a selected wordline after the first reference signal has stabilized and while the first sense current is applied to the first bitline.

Apparatus and method for accessing a magnetoresistive random access memory array

MRAM noise stabilizing and reducing apparatus and methods for MRAM sensing operations injects noise generated by activation of a word line ( ) into a sense line ( ) and a reference line ( ). Sense strings ( ) addressed by the word line ( ) are alternately coupled to the sense line ( ) and the reference line ( ). Cross coupling reduces the noise injected on the sense lines ( ). Cross coupling also balances the noise created by activation of the word line ( ) between the sense line ( ) and reference line ( ). A sense string ( ) not addressed by the word line ( ) provides a reference signal. A differential amplifier ( ) includes circuitry to compare and store a difference between the sense line ( ) and the reference line ( ). The stored value can be further compared to a second value obtained by reversing the current on the word line ( ).

Growing community of inventors

Plymouth, MN, United States of America

Wayne Theel