Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Socionext Inc.

Wataru Abe

Shuji Nakaya

Mitsuaki Hayashi

Masakazu Kurata

Hayashi Mitsuaki

Yutaka Terada

Yasuhiro Agata

Kenji Misumi

Mituaki Hayashi

A circuit on an end column of a divided memory array is formed by a block selection transistor having the same shape as that of a memory cell transistor. As the pattern of the connecting section between the main bit line and the sub-bit line is made in the same shape as that of the memory cell, it is possible to realize a pattern uniformity and to eliminate the need for using memory array dummy patterns.

Semiconductor memory device with a selection transistor having same shape and size as a memory cell transistor

Subarrays, which constitute a memory cell array, each include a bit line driving transistor having a drain connected to a bit line, a source is connected to an interconnection having a power supply potential, and a gate is connected to a sub-bit line. The plurality of memory cells are each provided in such away that a gate is connected to a word line, a source is grounded, and whether a drain is connected to the sub-bit line or not is selected in correspondence to data to be stored. Transmission transistors each have a gate connected to the bit line, a source connected to a loading transistor section, and a drain connected to the sub-bit line.

Semiconductor memory device

A semiconductor memory device includes a memory cell array, a charge circuit which compensates for OFF leakage current developed at selected bit lines, a reset circuit having a ground potential corresponding to a potential at non-selected bit lines, a read circuit constituted by a plurality of transistors whose gates are connected to the bit lines, and a bit line precharge circuit which charges the selected bit lines for a fixed time period. As a result of adopting such a configuration, there is no need to provide a transmission gate, such as a column decoder, to a charging path between the read circuit and the bit lines, so that a low-power supply voltage operation can be effected without the influence of a substrate bias effect.

Semiconductor memory device having bit line precharge circuit controlled by address decoded signals

In semiconductor memory devices having hierarchical bit line structures, a transfer transistor provided between a main bit line and a sub-bit line hinders achievement of a high speed and a low voltage. A sub-bit line SBL in a subarrayis connected via a first transistor PCto a power source voltage, and via a second transistor NCto a ground voltage. A main bit line MBLj is connected via a third transistor PDto the power source voltage. The gate electrodes of the first transistor PCand the second transistor NCare connected to the main bit line MBLj, the gate electrode of the third transistor PDis connected to the sub-bit line SBL. In an initial state, a voltage of the main bit line MBLj is controlled to be at an H level, and voltages of word lines WLito Wlip are controlled to be at an L level. When a read operation is performed, the voltage of the main bit line MBLj transitions to the L level, and thereafter, the voltage of a selected word line transitions to the H level.

Semiconductor memory device having a hierarchical bit line structure

A semiconductor memory device is provided which has a hierarchical bit line structure and can perform a high-speed read operation even with a low voltage. A subarrayincludes a first MOS transistor PDfor charging a main bit line MBLand a second MOS transistor PSfor charging a sub-bit line SBL. The source electrode of the second MOS transistor PSis connected to a power source voltage, and the source electrode of the first MOS transistor PDis connected via a fourth MOS transistor PDto the power source voltage. Since there is not a resistance between the main bit line MBLand the sub-bit line SBL, which is present if a transistor is used to achieve conduction therebetween, discharging of the main bit line and charging of the sub-bit line can be performed with high speed.

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Osaka, Japan

Wataru Abe