Intel Corporation

Tahoe Research, Ltd.

Warren Morrow

Pete D Vogt

Dennis W Brzezinski

Eric Dahlen

John B Halbert

Kenneth D Shoemaker

Peter D Vogt

Theodore L Willke

Andre Schaefer

Jin Kim

Andrew M Volk

Howard S David

Brandon Barnett

Robin A Steinbrecher

Stephen W Montgomery

David S De Lorenzo

Raman Nayyar

Jayamohan Dharanipathi

A stacked memory with interface providing offset interconnects. An embodiment of memory device includes a system element and a memory stack coupled with the system element, the memory stack including one or more memory die layers. Each memory die layer includes first face and a second face, the second face of each memory die layer including an interface for coupling data interface pins of the memory die layer with data interface pins of a first face of a coupled element. The interface of each memory die layer includes connections that provide an offset between each of the data interface pins of the memory die layer and a corresponding data interface pin of the data interface pins of the coupled element.

Stacked memory with interface providing offset interconnects

Dynamic operations for operations for a stacked memory with interface providing offset interconnects. An embodiment of memory device includes a system element and a memory stack coupled with the system element, the memory stack including one or more memory die layers. Each memory die layer includes first face and a second face, the second face of each memory die layer including an interface for coupling data interface pins of the memory die layer with data interface pins of a first face of a coupled element. The interface of each memory die layer includes connections that provide an offset between each of the data interface pins of the memory die layer and a corresponding data interface pin of the data interface pins of the coupled element.

Memory apparatus and methods utilizing multiple bit lanes may redirect one or more signals on the bit lanes. A memory agent may include a redrive circuit having a plurality of bit lanes, a memory device or interface, and a fail-over circuit coupled between the plurality of bit lanes and the memory device or interface.

Disabling outbound drivers for a last memory buffer on a memory channel

Memory channel with bit lane fail-over

An optical bus interconnects two or more processors in a multiprocessor system. One or more electrical-to-optical ('E-O') transmitters are optically coupled to the optical bus using optical couplers. The E-O transmitters receive electrical signals from the processors and convert the electrical signals to optical signals to be guided onto the optical bus. Optical-to-electrical ('O-E') receivers are also coupled to the optical bus using the optical couplers. The O-E receivers receive optical signals from the optical bus and convert the optical signals to electrical signals for the processors.

Optical add/drop interconnect bus for multiprocessor architecture

Some embodiments of the invention accurately account for power dissipation in memory systems that include individual memory modules by keeping track of the number of read requests, the number of write requests, and the number of activate requests that are applied to the individual memory modules during selected time periods. If the sum of these totals exceeds a threshold level, the embodiments throttle the memory system, either by throttling the entire memory system based in response to the most active memory module, or by throttling individual memory modules as needed. Other embodiments of the invention may assign the same or different weights to activate requests, read requests, and write requests. Other embodiments are described and claimed.

System and method for thermal throttling of memory modules

An electronic system includes a device and a controller to the device. The controller is adapted to calculate a temperature estimate of the device and to control access to the device in accordance with the calculated temperature estimate.

Method and apparatus for memory bandwidth thermal budgetting

In some embodiments, a system includes a first memory assembly coupled to a first channel and a second memory assembly coupled to a second channel. The system includes a memory controller to write first and second primary data sections to the first and second memory assemblies, respectively, and write first and second redundant data sections to the second and first memory assemblies, respectively, wherein the first and second redundant data sections are redundant with respect to the first and second primary data sections, respectively. Other embodiments are described and claimed.

Interleaved mirrored memory systems

In some embodiments, a memory controller includes first and second memory channel interfaces and memory access control circuitry. The memory access control circuitry is to send first and second primary data sections to the first and second memory channel interfaces, respectively, and send first and second redundant data sections to the second and first memory channel interfaces, respectively. The first and second redundant data sections are redundant with respect to the first and second primary data sections, respectively. Other embodiments are described and claimed.

Growing community of inventors

Steilacoom, WA, United States of America

Warren Morrow