Globalfoundries Inc.

Wanxun He

Xusheng Kevin Wu

Changyong Xiao

Xiang Hu

Hongliang Shen

Manfred Eller

Jie Chen

A non-planar semiconductor structure includes raised semiconductor structures, e.g., fins, having epitaxial structures grown on top surfaces thereof, for example, epitaxial silicon naturally growing into a diamond shape. The surface area of the epitaxial structure may be increased by removing portion(s) thereof. The removal may create a multi-head (e.g., dual-head) epitaxial structure, together with the neck of the raised structure resembling a Y-shape. Raised structures that are not intended to include an epitaxial structure will be masked during epitaxial structure creation and modification. In addition, in order to have a uniform height, the filler material surrounding the raised structures is recessed around those to receive epitaxial structures.

Non-planar semiconductor device with multiple-head epitaxial structure on fin

A non-planar semiconductor structure includes mixed n-and-p type raised semiconductor structures, e.g., fins, having epitaxial structures grown on top surfaces thereof, for example, epitaxial silicon and silicon germanium, naturally growing into a diamond shape. The surface area of the epitaxial structures is increased by removing portion(s) thereof, masking each type as the other type is grown and then subsequently modified by the removal. The removal may create multi-head (e.g., dual-head) epitaxial structures, together with the neck of the respective raised structure resembling a Y-shape.

Mixed N/P-type fin semiconductor structure with epitaxial materials having increased surface area through multiple epitaxial heads

Method for increasing a surface area of epitaxial structures in a mixed N/P type fin semiconductor structure by forming multiple epitaxial heads

An integrated circuit product is disclosed that includes a plurality of trenches in a semiconducting substrate that define first, second and third fins, wherein the fins are side-by-side, and wherein the second fin is positioned between the first and third fins, a layer of insulating material in the plurality of trenches such that a desired height of the first, second and third fins is positioned above an upper surface of the layer of insulating material, a recess defined in the second fin that at least partially defines a cavity in the layer of insulating material, an SDB isolation structure in the cavity on the recessed portion of the second fin, wherein the SDB isolation structure has an upper surface that is above the upper surface of the layer of insulating material, and a gate structure for a transistor positioned above the SDB isolation structure.

Product comprised of FinFET devices with single diffusion break isolation structures

One illustrative method disclosed herein includes, among other things, forming first, second and third fins that are arranged side-by-side, forming a recessed layer of insulating material in a plurality of trenches, after recessing the layer of insulating material, masking the first and second fins while exposing a portion of the axial length of the second fin, removing the exposed portion of the second fin so as to thereby define a cavity in the recessed layer of insulating material, forming an SDB isolation structure in the cavity, wherein the SDB isolation structure has an upper surface that is positioned above the recessed upper surface of the recessed layer of insulating material, removing the masking layer, and forming a gate structure for a transistor above the SDB isolation structure.

Product comprised of FinFET devices with single diffusion break isolation structures, and methods of making such a product

Embodiments of the present invention provide an improved method for fabrication of fin field effect transistors (finFETs). Sacrificial regions are formed on a semiconductor substrate. Spacers are formed adjacent to two sides of the sacrificial regions. Fins are formed based on the spacers. One set of spacers is treated as dummy spacers, and is removed prior to fin formation, leaving the other set of spacers to be used for forming fins on the final semiconductor structure. All the fins on the final semiconductor structure are formed from spacers on one side of the sacrificial material. This reduces variation in width of the fins.

FinFET fabrication method

A method for forming FinFETs with reduced series resistance includes providing an intermediate semiconductor structure comprising a semiconductor substrate, a fin disposed on the semiconductor substrate, a gate disposed over a first portion of the fin, and a first sidewall spacer disposed over the fin and adjacent to the gate, increasing epitaxially the thickness of a second portion of the fin disposed outside the gate and the first sidewall spacer, and forming a second sidewall spacer disposed over the second portion of the fin and adjacent to the first sidewall spacer. A thickness of the second portion of the fin disposed under the second spacer is equal to or greater than a thickness of the first portion of the fin disposed under the gate.

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Mechanicville, NY, United States of America

Wanxun He