Taiwan Semiconductor Manufacturing Comp. Ltd.

Wang-Pen Mo

Hung-Chang Hsieh

Chun-Wei Chang

Chun-Chang Chen

Chih-Chien Wang

Shih-Chi Fu

Chuan-Ling Wu

Shun-Shing Yang

Hong-Da Lin

Chia-Shiung Tsai

Yeur-Luen Tu

Jhy-Jyi Sze

Cheng-Ta Wu

Jiech-Fun Lu

Feng-Jia Shiu

Hung Chang Hsieh

Chia-Chieh Lin

Chung Chien Wang

Chihy-Yuan Cheng

Chu-Wei Chang

Cheng-Hsien Chuang

A method for forming a photoresist layer on a semiconductor device is disclosed. An exemplary includes providing a wafer. The method further includes spinning the wafer during a first cycle at a first speed, while a pre-wet material is dispensed over the wafer and spinning the wafer during the first cycle at a second speed, while the pre-wet material continues to be dispensed over the wafer. The method further includes spinning the wafer during a second cycle at the first speed, while the pre-wet material continues to be dispensed over the wafer and spinning the wafer during the second cycle at the second speed, while the pre-wet material continues to be dispensed over the wafer. The method further includes spinning the wafer at a third speed, while a photoresist material is dispensed over the wafer including the pre-wet material.

Method of forming a photoresist layer

A method includes forming a first photo resist layer over a base structure and a target feature over the base structure, performing an un-patterned exposure on the first photo resist layer, and developing the first photo resist layer. After the step of developing, a corner portion of the first photo resist layer remains at a corner between a top surface of the base structure and an edge of the target feature. A second photo resist layer is formed over the target feature, the base structure, and the corner portion of the first photo resist layer. The second photo resist layer is exposed using a patterned lithography mask. The second photo resist layer is patterned to form a patterned photo resist.

Lithography process on high topology features

A method for preparing a wafer includes forming a film layer on a substrate of the wafer; coating the film layer with a photoresist layer; exposing a first portion of the photoresist layer to a beam of light; and patterning a second portion of the photoresist layer after performing exposing the first portion of the photoresist layer. A cross-link reaction is caused on the first portion of the photoresist layer and the first portion of the photoresist layer is converted to a reacted first portion of the photoresist layer. The reacted first portion of the photoresist layer is near an edge of the wafer. The second portion of the photoresist layer is different from the reacted first portion of the photoresist layer. The second portion of the photoresist layer is converted to a patterned second portion of the photoresist layer.

Film portion at wafer edge

A film layer on a substrate of the wafer is patterned to form a first plurality of areas of the film layer and a second plurality of areas of the film layer. The first plurality of areas of the film layer is removed. The second plurality of areas of the film layer is kept on the substrate. A first portion of the film layer is kept on the substrate. A first edge of the first portion of the film layer is substantially near an edge of the wafer. The first portion of the film layer defines a boundary for the wafer.

Among other things, one or more techniques and systems for performing a spin coating process associated with a wafer and for controlling thickness of a photoresist during the spin coating process are provided. In particular, a thickening phase is performed during the spin coating process in order to increase a thickness of the photoresist. For example, air temperature of down flow air, flow speed of the down flow air, and heat temperature of heat supplied towards the wafer are increased during the thickening phase. The increase in down flow air and heat increase a vaporization factor of the photoresist, which results in an increase in viscosity and thickness of the photoresist. In this way, the wafer can be rotated at relatively lower speeds, while still attaining a desired thickness. Lowering rotational speed of wafers allows for relatively larger wafers to be stably rotated.

Thickening phase for spin coating process

A method of fabricating integrated circuit devices is provided. The method includes forming a plurality of spaced integrated circuit dies on a semiconductor wafer and forming a dedicated test die on the semiconductor wafer adjacent the plurality of spaced integrated circuit dies, the dedicated test die including a test structure having a first width when viewed in a top view and being operable to generate wafer evaluation data. Further, the method includes forming a scribe line region interposed between the plurality of spaced integrated circuit dies, the scribe line region having a second width defined by a distance between adjacent integrated circuit dies when viewed in a top view, the second width being smaller than the first width, and the scribe line region being free of test structures.

Test structure placement on a semiconductor wafer

A method for manufacturing the image sensor device is provided. The method includes depositing a first dielectric layer over a back surface of a substrate, forming a ridge over the first dielectric layer, depositing a second dielectric layer over the first dielectric layer, including filling in a space between two adjacent ridges. The method also includes removing the ridge to form a trench in the second dielectric layer and forming a metal grid in the trench.

Method of fabricating a metal grid for semiconductor device

A method includes forming a plurality of image sensors on a front side of a semiconductor substrate, and forming a dielectric layer on a backside of the semiconductor substrate. The dielectric layer is over the semiconductor substrate. The dielectric layer is patterned into a plurality of grid-filling regions, wherein each of the plurality of grid-filling regions overlaps one of the plurality of image sensors. A metal layer is formed on top surfaces and sidewalls of the plurality of grid-filling regions. The metal layer is etched to remove horizontal portions of the metal layer, wherein vertical portions of the metal layer remain after the step of etching to form a metal grid. A transparent material is filled into grid openings of the metal grid.

Metal grid in backside illumination image sensor chips and methods for forming the same

A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate having two different topography areas adjacent to each other. A step-forming material (SFM) is deposited over the substrate. A patterned SFM is formed in the low topography area of the two areas. The formation of the patterned SFM provides a fairly planar surface across over the substrate.

Method of semiconductor integrated circuit fabrication

Some embodiments relate to a method for processing a workpiece. In the method, an anti-reflective coating layer is provided over the workpiece. A first patterned photoresist layer, which has a first photoresist tone, is provided over the anti-reflective coating layer. A second patterned photoresist layer, which has a second photoresist tone opposite the first photoresist tone, is provided over the first patterned photoresist layer. An opening extends through the first and second patterned photoresist layers to allow a treatment to be applied to the workpiece through the opening. Other embodiments are also disclosed.

Manufacturing techniques for workpieces with varying topographies

The present disclosure relates to a method and composition to limit crystalline defects introduced in a semiconductor device during ion implantation. A high-temperature low dosage implant is performed utilizing a tri-layer photoresist which maintains the crystalline structure of the semiconductor device while limiting defect formation within the semiconductor device. The tri-layer photoresist comprises a layer of spin-on carbon deposited onto a substrate, a layer of silicon containing hard-mask formed above the layer of spin-on carbon, and a layer of photoresist formed above the layer of silicon containing hard-mask. A pattern formed in the layer of photoresist is sequentially transferred to the silicon containing hard-mask, then to the spin-on carbon, and defines an area of the substrate to be selectively implanted with ions.

Method to form a CMOS image sensor

Semiconductor devices and manufacturing methods thereof are disclosed. In one embodiment, a semiconductor device includes a workpiece with a first region having a plurality of first features and a second region having a plurality of second features proximate the first region. The first region and the second region share a patterning overlap region disposed between the first region and the second region. The patterning overlap region includes a residue feature with an aspect ratio of about 4 or less.

Semiconductor devices and manufacturing methods thereof

Some embodiments relate to a method for processing a workpiece. In the method, a first photoresist layer is provided over the workpiece, wherein the first photoresist layer has a first photoresist tone. The first photoresist layer is patterned to provide a first opening exposing a first portion of the workpiece. A second photoresist layer is then provided over the patterned first photoresist layer, wherein the second photoresist layer has a second photoresist tone opposite the first photoresist tone. The second photoresist layer is then patterned to provide a second opening that at least partially overlaps the first opening to define a coincidentally exposed workpiece region. A treatment is then performed on the coincidentally exposed workpiece region. Other embodiments are also disclosed.

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Pingtung, Taiwan

Wang-Pen Mo