Globalfoundries Singapore Pte. Ltd.

Globalfoundries Inc.

Agency for Science, Technology and Research

Alsephina Innovations Inc.

Wanbing Yi

Juan Boon Tan

Yi Jiang

Curtis Chun-I Hsieh

Danny Pak-Chum Shum

Bharat Bhushan

Mahesh Bhatkar

Wei-Hui Hsu

Hai Cong

Wei Shao

Kai Kang

Soh Yun Siah

Benfu Lin

Ming Zhu

Wei Liu

Alex See

Darin A Chan

Ramasamy Chockalingam

Pinghui Li

Shunqiang Gong

Luke G England

Lup San Leong

Kangho Lee

Kiok Boone Elgin Quek

Khee Yong Lim

Wei Lu

Jeoung Mo Koo

Chim Seng Seet

Shaoqiang Zhang

Yongshun Sun

Daxiang Wang

Chin Chuan Neo

Pak-Chum Danny Shum

Bhushan Bharat

Neha Nayyar

Shan Gao

Ee Jan Khor

Boo Yang Jung

Hyunwoo Yang

Cing Gie Lim

Zhehui Wang

Young Seon You

Liying Zhang

Haiqing Zhou

Wenjun Liu

Francis Yong Wee Poh

Tze Ho Simon Chan

Weining Li

Bong Woong Mun

Lei Wang

Yang Hong

Yiang Aun Nga

Lulu Peng

Jianxun Sun

Francis YongWee Poh

Kin Wai Tang

Haifeng Sheng

Jens Oswald

Teck Guan Lim

Hui Liu

Tupei Chen

Chao Zhu

Eng-Huat Toh

Kemao Lin

Kwang Sing Yew

Hari Balan

Wei Yi Lim

Rajesh Nair

Chun-I Hsieh

Michael Han Kim Kwong

Eva Wai Leong Ching

Qian Chen

Suleni Tunggal Mulia

Yongmei Hu

Gong Shun Qiang

The present disclosure relates to semiconductor structures and, more particularly, to capacitor structures and methods of manufacture. The structure includes: an airgap provided within a dielectric material; an insulator material across a top of the airgap and on a surface of the dielectric material; and a capacitor provided within the dielectric material and lined with the insulator material.

Capacitor and airgap structure

Structures for a static random access memory bit cell and methods of forming a structure for a static random access memory bit cell. The structure includes a first field-effect transistor on a first substrate and a second field-effect transistor on a second substrate. The first field-effect transistor includes a first gate, and the second field-effect transistor includes a second gate. The structure further includes a first interconnect structure on the first substrate and a second interconnect structure on the second substrate. The first interconnect structure includes a first metal feature connected to the first gate, and the first metal feature has a first surface. The second interconnect structure includes a second metal feature connected to the second gate, and the second metal feature has a second surface that is connected to the first surface of the first metal feature.

SRAM bit cells with three-dimensional integration

The present disclosure generally relates to memory devices and methods of forming the same. More particularly, the present disclosure relates to resistive random-access (ReRAM) memory devices incorporating reference cells for achieving high sensing yield. The present disclosure provides a memory device including a main cell structure including a switching element arranged between a pair of conductors, and a reference cell structure electrically coupled to the main cell structure. The reference cell structure includes a switching element arranged between a pair of conductors, in which the switching element of the reference cell structure has a dimension that is different from a dimension of the switching element of the main cell structure.

Memory devices and methods of forming the same

A structure includes a galvanic isolation including a horizontal portion including a first redistribution layer (RDL) electrode in a first insulator layer, and a second RDL electrode in the first insulator layer laterally spaced from the first RDL electrode. An isolation break includes a trench defined in the first insulator layer between the first RDL electrode and the second RDL electrode, and at least one second insulator layer in the trench. The first insulator layer and the second insulator layer(s) are between the first RDL electrode and the second RDL electrode. The isolation may separate, for example, voltage domains having different voltage levels. A related method is also disclosed. The isolation may also include a vertical portion using the first RDL electrode and another electrode in a metal layer separated from the first RDL electrode by a plurality of interconnect dielectric layers.

Galvanic isolation using isolation break between redistribution layer electrodes

A resistive memory device is provided. The resistive memory device comprises a first metal oxide layer above a body electrode. A correlated electron layer located between a source and a drain and above the first metal oxide layer. A gate above a bottom portion of the correlated electron layer.

Correlated electron resistive memory device and integration schemes

According to various embodiments, there is provided a memory cell. The memory cell may include a transistor, a dielectric member, an electrode and a contact member. The dielectric member may be disposed over the transistor. The electrode may be disposed over the dielectric member. The contact member has a first end and a second end opposite to the first end. The first end is disposed towards the transistor, and the second end is disposed towards the dielectric member. The contact member has a side surface extending from the first end to the second end. The second end may have a recessed end surface that has a section that slopes towards the side surface so as to form a tip with the side surface at the second end. The dielectric member may be disposed over the second end of the contact member and may include at least a portion disposed over the tip.

Memory cells and methods for forming memory cells

An illustrative device disclosed herein includes a bottom electrode, a conformal switching layer positioned above the bottom electrode and a top electrode positioned above the conformal switching layer. The top electrode includes a conformal layer of conductive material positioned above the conformal switching layer and a conductive material positioned above the conformal layer of conductive material.

Resistive memory device and methods of making such a resistive memory device

The present disclosure generally relates to memory devices and methods of forming the same. More particularly, the present disclosure relates to resistive random-access (ReRAM) memory devices. The present disclosure provides a memory device including an opening in a dielectric structure, the opening having a sidewall, a first electrode on the sidewall of the opening, a spacer layer on the first electrode, a resistive layer on the first electrode and upon an upper surface of the spacer layer, and a second electrode on the resistive layer.

Resistive random access memory devices

A semiconductor device may be provided, including a base layer, an insulating layer arranged over the base layer, a memory structure arranged at least partially within the insulating layer, where the memory structure may include a first electrode, a second electrode, and an intermediate element between the first electrode and the second electrode, and a resistor arranged at least partially within the insulating layer, where the resistor may be arranged in substantially a same horizontal plane with one of the first electrode and the second electrode.

Semiconductor devices and methods of forming semiconductor devices

A memory device may be provided, including a base layer; an insulating layer arranged over the base layer, where the insulating layer may include a recess having opposing side walls; a first electrode arranged along the opposing side walls of the recess; a switching element arranged along the first electrode; a second electrode arranged along the switching element; and a capping layer arranged over the recess, where the capping layer may at least partially overlap the first electrode, the switching element and the second electrode.

Memory devices and methods of forming memory devices

A device and methods for forming the device is provided. The device includes a substrate and circuit elements thereon. The device further includes a metallization layer over the substrate. The metallization layer includes interconnects interconnecting the circuit elements. A test pad is disposed over an uppermost interconnect in the metallization layer. The test pad is coupled to one or more circuit elements via the interconnects. The test pad is configured for testing the one or more circuit elements. A crack stop protection seal surrounding the test pad is provided. The crack stop protection seal confines damage caused by probing at the test pad from propagating to an area beyond the crack stop protection seal.

Test pad with crack stop protection

Integrated circuits with embedded memory structures, and methods for fabricating integrated circuits are provided. An exemplary method for fabricating an integrated circuit includes forming from a first metallization layer a first lower conductive interconnect in a first region of a dielectric layer and a second lower conductive interconnect in a second region of the dielectric layer. The method includes forming a memory structure in the first region. Further, the method includes depositing an interlayer dielectric over the first region and over the second region. Also, the method includes forming from a second metallization layer a first upper conductive interconnect over the interlayer dielectric, wherein the first upper conductive interconnect is coupled to the memory structure.

Integrated circuits with embedded memory structures and methods for fabricating the same

The present disclosure generally relates to memory devices and methods of forming the same. More particularly, the present disclosure relates to resistive random-access (ReRAM) memory devices incorporating reference cells for achieving high sensing yield. The present disclosure provides a memory device including a main cell structure having a dimension, and a reference cell structure electrically coupled to the main cell structure. The reference cell structure has a dimension that is different from the dimension of the main cell structure, in which the main cell structure and the reference cell structure include a switching element arranged between a pair of conductors.

A memory device may be provided, including a base layer, an insulating layer, a first electrode, a switching element, a capping element and a second electrode. The insulating layer may be arranged over the base layer and may include a recess having opposing side walls. The first electrode may be arranged at least partially within the recess of the insulating layer and along the opposing side walls of the recess of the insulating layer. The switching element may be arranged at least partially within the recess of the insulating layer and along the first electrode. The capping element and the second electrode may be arranged at least partially within the recess of the insulating layer. The capping element may be arranged between the second electrode and the switching element, and a part of the second electrode may extend across the capping element to contact the switching element.

A method of forming a uniform self-aligned low-k layer with a large process window for inserting a memory array with pillar/convex topography and the resulting device are provided. Embodiments include forming a substrate with a first region and a second region; forming a first low-K layer over the substrate; forming an oxide layer over the first low-K layer; forming a spacer over the oxide layer; etching the spacer to expose the oxide layer in the first region; removing the oxide layer and a portion of the first low-K layer in the first region and a portion of the oxide layer and a portion of the spacer in the second region; removing the spacer in the second region; cleaning the first low-K layer and the oxide layer, a triangular-like shaped portion of the oxide layer remaining; and forming a second low-K layer over the substrate.

Self-aligned planarization of low-k dielectrics and method for producing the same

Growing community of inventors

Singapore, Singapore

Wanbing Yi