Worldwide Semiconductor Manufacturing Corporation

Wan Yih Lien

Kung Linliu

Meng-Jaw Cherng

A method for forming salicide on the peripheral logic region of the embedded DRAM without using a salicide block mask layer to protect the memory cell region of the embedded DRAM and without oxide wet dip to prevent oxide loss in the field oxide is disclosed. Additionally, the landing plug process in the memory cell region is performed by a self-aligned contact (SAC) etching process with a silicon nitride layer as an etching protective layer.

Method to fabricate embedded DRAM with salicide logic cell structure

A method for forming a DRAM cell of a DRAM circuit is disclosed. The DRAM circuit includes a periphery region and a cell region. The DRAM cell is in the cell region and comprises an access transistor and a capacitor. The access transistor has a gate, a source, and a drain. The periphery region includes a plurality of gates. The method comprises the deposition of a silicon oxynitride layer over the gates, the silicon oxynitride layer acting as a bottom anti-reflection coating. That portion of the silicon oxynitride layer that lies over the DRAM cell is removed. A landing pad is formed over the source of the access transistor and a bitline pad is formed over the drain of the transistor. Next, a first oxide layer is formed over the landing pad and the bitline pad. A capacitor is formed over the landing pad and a second oxide layer is formed over the capacitor. Finally, metal contacts are formed to at least one of the gates in the periphery region using the silicon oxynitride layer as a buffer layer to prevent substrate loss or overetching.

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Hsinchu, Taiwan

Wan Yih Lien