Yc Corporation

Wan Soon Park

Yong Hyun Kim

Hyo Sang Jo

Jae Hoon Joo

A semiconductor test apparatus comprises a failure memory (FM) block configured to store failure data generated from a result of testing a semiconductor device, a buffer memory (BM) block to/in which the failure data stored in the FM block is configured to be copied/stored, and a field programmable gate array (FPGA) configured to perform a first control operation to control the FM block and a second control operation to control the BM block.

Semiconductor test apparatus using FPGA and memory control method for semiconductor test

A semiconductor test apparatus is provided. The semiconductor test apparatus includes: a test management unit determining a test mode, generating a test signal in accordance with the determined test mode, and transmitting the test signal to fail memories; and one or more fail memory boards including the fail memory, which store fail signals generated as a result of a test conducted in accordance with the test signal and address information of the fail signals, wherein if the determined test mode is a first test mode, at least some of the failure memory boards are powered off.

Growing community of inventors

Yongin-si, South Korea

Wan Soon Park