Intel Corporation

Wai Loon Yip

Michael T Klinglesmith

Terrence Huat Hin Tan

Rehan M Sheikh

Deepak Rameshkumar Tanna

Sukhbinder Takhar

Kok Hin Oon

Yudhishthira Kundu

Shi Hou Chong

Disclosed herein are structures and techniques for exposing circuitry in die testing. For example, in some embodiments, an integrated circuit (IC) die may include: first conductive contacts at a first face of the die; second conductive contacts at a second face of the die; die stack emulation circuitry; other circuitry; and a switch coupled to the second conductive contacts, the die stack emulation circuitry, and the other circuitry, wherein the switch is to couple the second conductive contacts to the other circuitry when the switch is in a first state, and the switch is to couple the die stack emulation circuitry to the other circuitry when the switch is in a second state different from the first state.

Die stack override for die testing

Growing community of inventors

Penang, Malaysia

Wai Loon Yip