Texas Instruments Corporation

Hitachi, Ltd.

Wah Kit Loh

Xiaowei Deng

Anand Seshadri

Theodore Warren Houston

Danny R Cline

Hugh Pryor McAdams

Shaofeng Yu

Beena Pious

Parvinder Kumar Rana

Theo J Powell

Russell Carlton McMullan

Terence G W Blake

Jon Lescrenier

Goro Kitsukawa

Takesada Akiba

Donald J Redwine

Masayuki Nakamura

Jeffrey E Koelling

Hiroshi Otori

Dharin Nayeshbhai Shah

Ching-Yuh Tsay

Zhonghai Shi

Kemal Tamer San

Kuong Hua Hii

Stanton Petree Ashburn

Adin E Hyslop

Lakshmikantha V Holla

Narasimhan Iyengar

Jayesh C Raval

Md Abul Bashar Khan

Yang Yi

Chok Y Hung

Kuong H Hii

A method of screening complementary metal-oxide-semiconductor CMOS integrated circuits, such as integrated circuits including CMOS static random access memory (SRAM) cells, for transistors susceptible to transistor characteristic shifts over operating time. For the example of SRAM cells formed of cross-coupled CMOS inverters, separate ground voltage levels can be applied to the source nodes of the driver transistors, or separate power supply voltage levels can be applied to the source nodes of the load transistors (or both). Asymmetric bias voltages applied to the transistors in this manner will reduce the transistor drive current, and can thus mimic the effects of bias temperature instability (BTI). Cells that are vulnerable to threshold voltage shift over time can thus be identified.

Array power supply-based screening of static random access memory cells for bias temperature instability

A static random-access memory (SRAM) in an integrated circuit with circuitry for timing the enabling of sense amplifiers. The memory includes read/write SRAM cells, along with word-line tracking transistors arranged in one or more rows along a side of the read/write cells, and read-tracking transistors arranged in a column along a side of the read/write cells. A reference word line extends over the word-line tracking transistors, with its far end from the driver connected to pass transistors in the read-tracking transistors. The read-tracking transistors are preset to a known data state that, when accessed responsive to the reference word line, discharges a reference bit line, which in turn drives a sense amplifier enable signal.

Read-current and word line delay path tracking for sense amplifier enable timing

An SRAM with buffered-read bit cells is disclosed (FIGS.-). The integrated circuit includes a plurality of memory cells (). Each memory cell has a plurality of transistors (). A first memory cell (FIG.) is arranged to store a data signal in response to an active write word line (WWL) and to produce the data signal in response to an active read word line (RWL). A test circuit () formed on the integrated circuit is operable to test current and voltage characteristics of each transistor of the plurality of transistors of the first memory cell (FIGS.-).

SRAM with buffered-read bit cells and its testing

An integrated circuit containing a memory and a sense amplifier. The integrated circuit also containing an extended delay circuit which extends the delay between when a precharged bitline is floated and when a wordline is enabled. A method of testing an integrated circuit to identify bitlines with excessive leakage.

Bitline leakage detection in memories

A method of testing large-scale integrated circuits including multiple instances of memory arrays, and an integrated circuit structure for assisting such testing. In one embodiment, voltage drops due to parasitic resistance in array bias conductors are determined by extracting layout parameters, and subsequent circuit simulation that derives the voltage drops in those conductors during operation of each memory array. In another embodiment, sense lines from each memory array are selectively connected to a test sense terminal of the integrated circuit, at which the array bias voltage at each memory array is externally measured. Feedback control of the applied voltage to arrive at the desired array bias voltage can be performed.

Functional screening of static random access memories using an array bias voltage

An integrated circuit on-chip parametric (OCP) test structure includes a static random access memory (SRAM) universal test structure (UTS) having UTS ports and an OCP controller configured to determine first and second UTS ports of the SRAM UTS for independent connection to first and second on-chip test pads, respectively. The integrated circuit OCP test structure further includes a UTS OCP router connected to the OCP controller and configured to connect the first and second UTS ports of the SRAM UTS to the first and second on-chip test pads, respectively. Methods of operating an integrated circuit OCP test structure and OCP testing of an integrated circuit are also included.

Universal test structures based SRAM on-chip parametric test module and methods of operating and testing

An integrated circuit containing an SAR SRAM and CMOS logic, in which sidewall spacers on the gate extension of the SAR SRAM cell are thinner than sidewall spacers on the logic PMOS gates, so that the depth of the drain node SRAM PSD layer is maintained under the stretch contact. A process of forming an integrated circuit containing an SAR SRAM and CMOS logic, including selectively etch the sidewall spacers on the on the gate extension of the SAR SRAM cell, so that the depth of the drain node SRAM PSD layer is maintained under the stretch contact. A process of forming an integrated circuit containing an SAR SRAM and CMOS logic, including selectively implanting extra p-type dopants in the drain node SRAM PSD layer, so that the depth of the drain node SRAM PSD layer is maintained under the stretch contact.

CMOS process to improve SRAM yield

A method of screening complementary metal-oxide-semiconductor CMOS integrated circuits, such as integrated circuits including CMOS static random access memory (SRAM) cells, for n-channel transistors susceptible to transistor characteristic shifts over operating time. For the example of SRAM cells formed of cross-coupled CMOS inverters, static noise margin and writeability (V) screens are provided. Each of the n-channel transistors in the CMOS SRAM cells are formed within p-wells that are isolated from p-type semiconductor material in peripheral circuitry of the memory and other functions in the integrated circuit. Forward and reverse body node bias voltages are applied to the isolated p-wells of the SRAM cells under test to determine whether such operations as read disturb, or write cycles, disrupt the cells under such bias. Cells that are vulnerable to threshold voltage shift over time can thus be identified.

Method of screening static random access memory cells for positive bias temperature instability

A method of programming a memory array having plural subarrays is disclosed. (FIG.). The method includes determining a minimum operating voltage (Vmin) for each subarray of the plural subarrays (). A first voltage is applied to each subarray having a minimum operating voltage greater than a predetermined voltage (). A second voltage is applied to each subarray having a minimum operating voltage less than the predetermined voltage (and).

SRAM power reduction through selective programming

An integrated circuit including a complementary metal-oxide-semiconductor (CMOS) static random access memory (SRAM) with periodic deep well structures within the memory cell array. The deep well structures are contacted by surface well regions of the same conductivity type (e.g., n-type) in the memory cell array, forming two-dimensional grids of both n-type and p-type semiconductor material in the memory cell array area. Bias conductors may contact the grids to apply the desired well bias voltages, for example in well-tie regions or peripheral circuitry adjacent to the memory cell array.

Static random-access memory cell array with deep well regions

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Richardson, TX, United States of America

Wah Kit Loh