Infineon Technologies Ag

Wae Chet Yong

Stanley Job Doraisamy

Teck Sim Lee

Khai Huat Jeffrey Low

Chai Wei Heng

Gerhard Deml

Bernd Goller

Chau Fatt Chiang

Markus Dinkel

Stefan Macheiner

Khay Chwan Saw

Boon Kian Lim

Joachim Mahler

Petteri Palm

Thomas Bemmerl

Erich Griebl

Juergen Schredl

Chee Yang Ng

Reimund Engl

Theng Chao Long

Josef Maerz

Sergey Yuferev

Soon Hock Tong

Rupert Fischer

Mario Feldvoss

Tien Lai Tan

Wee Boon Tay

Bun Kian Tay

Kuok Wai Chan

Christoph Liebl

Mohd Fauzi Hj Mahat

Paul Armand Asentista Calo

A package and method of manufacturing a package is disclosed. In one example, a package which comprises a first transistor chip having a first source pad and a second transistor chip having a second source pad and being stacked with the first transistor chip at an interface area. The first source pad and the second source pad are coupled at the interface area.

Stacked transistor chip package with source coupling

A packaged semiconductor includes an electrically insulating encapsulant body having an upper surface, a first semiconductor die encapsulated within the encapsulant body, the first semiconductor die having a main surface with a first conductive pad that faces the upper surface of the encapsulant body, a second semiconductor die encapsulated within the encapsulant body and disposed laterally side by side with the first semiconductor die, the second semiconductor die having a main surface with a second conductive pad that faces the upper surface of the encapsulant body, and a first conductive track that is formed in the upper surface of the encapsulant body and electrically connects the first conductive pad to the second conductive pad. The encapsulant body includes a laser activatable mold compound.

Chip to chip interconnect in encapsulant of molded semiconductor package

A leadless package includes an at least partially electrically conductive carrier having a mounting section and a lead section, an electronic chip mounted on the mounting section, and an encapsulant at least partially encapsulating the electronic chip and partially encapsulating the carrier so that at least part of an interior sidewall of the lead section not forming part of an exterior sidewall of the package is exposed.

Encapsulated leadless package having an at least partially exposed interior sidewall of a chip carrier

A method of fabricating a semiconductor package. In one embodiment the method includes forming a mold cavity about a portion of a first major surface of a leadframe, including about a mold lock opening extending through the leadframe between the first major surface and a second major surface. A spacer is inserted to fill at least a portion of the mold lock opening. The mold cavity is filled with an encapsulating material including filling a portion of the mold lock opening not occupied by the spacer.

Method of fabricating a semiconductor package with mold lock opening

A semiconductor device including: a die pad, a die on the die pad, and resin encapsulating the die and forming an isolation thickness over the die pad, the resin including a mounting aperture and a major surface configured for mounting to an external device, the major surface having a non warpage compensation portion adjacent the die and a warpage compensation portion in a relatively thermally inactive zone with an approximate discontinuity and/or abrupt change in gradient between the non warpage compensation portion and the warpage compensation portion.

Method of fabricating a semiconductor device having a resin with warpage compensated structures

An electronic component includes a lead frame assembly, an insert, a semiconductor chip and an encapsulation compound. The lead frame assembly includes a mounting hole, a die pad, a plurality of bonding fingers and a plurality of lead fingers. The insert includes a hollow center and is provided at the mounting hole of the lead frame assembly. The semiconductor chip is arranged on the die pad and includes contact areas on its surface. A plurality of electrical contacts respectively links the contact areas of the semiconductor chip to the bonding fingers of the lead frame assembly. An encapsulating compound encloses the insert, the semiconductor chip, and the electrical contacts, however, leaves the hollow center of the insert uncovered.

Electronic component and a method of fabricating an electronic component

A transistor outline package is provided for a semiconductor integrated device suitable for use in a control module of an automobile for connection between a printed circuit board and a bus bar of such a module. The package includes a package housing, having a first end suitable for mounting to a PCB and which has a width. The package is also formed with a leadframe which includes a heat sink and ground plane blade suitable for connection to a bus bar, a plurality of connector leads suitable for connection to a PCB and at least one source tab lead suitable for connection to a module connector of such a control module. The plurality of connection leads and the source tab lead extend from the first end of the package housing side by side in the direction along and within the width of the first end of the package housing.

Integrated semiconductor outline package

A semiconductor device includes a carrier, a semiconductor chip including an active area on a first face and a separate isolation layer applied to a second face, and an adhesion material coupling the isolation layer to the carrier with the second face facing the carrier.

Semiconductor device including isolation layer

Semiconductor devices having a resin with warpage compensated surfaces

A semiconductor device including: a heat sink, a die on the heat sink, resin encapsulating the die, and a mounting aperture in the resin having at least a segment between the heat sink and a first end of the resin, wherein the thickness of the heat sink is no greater than 35% of the thickness of the device.

Semiconductor device

A semiconductor component and method for producing. The semiconductor component includes a semiconductor device and a leadframe. A package layout is defined and the orientation of electrically conductive members with respect to the semiconductor device and inner contact areas of the leadframe is altered so as to maximize the interfacial bonding area. The constraints of the standard package dimensions and the component assembly method are taken into account.

Semiconductor component having maximized bonding areas of electrically conductive members connected to semiconductor device and connected to leadframe and method of producing

A semiconductor package including a leadframe having first and second major surfaces and a mold lock opening extending between the first and second major surfaces. The semiconductor package includes a semiconductor die coupled to the first major surface, and an encapsulating material formed about the semiconductor chip and a portion of the first major surface of the leadframe and filling all but a portion of the mold lock opening, the unfilled portion of the mold lock opening forming a vent extending from the second major surface to the first major surface, the vent providing a pathway for air to escape from between the second major surface and a surface to which the second major surface is to be attached.

Semiconductor package with mold lock vent

There is provided a method of forming a component package. The method includes the steps of providing the die pad or heat sink, forming an isolation layer on the rear surface of the die pad or heat sink and encapsulating the die pad with encapsulating material in a mold cavity after forming the isolation layer on the rear of the die pad or heat sink.

Growing community of inventors

Malacca, Malaysia

Wae Chet Yong