Xilinx, Inc.

W Story Leavesley, Iii

Emil S Ochotta

William W Stiehl

Jay T Young

Jeffrey M Mason

Eric M Shiflet

Jason J Moore

Sandor S Kalman

Sankaranarayanan Srinivasan

Brendan K Bridgford

Jaime D Lujan

Douglas P Wieland

George L McHugh

Derrick S Woods

Brian J Alexander

William R Bell, Ii

A method of processing a logical netlist for implementing a circuit design within a programmable integrated circuit includes identifying a dynamically reconfigurable module (DRM) comprising a port from the logical netlist. The DRM defines a dynamically reconfigurable region of the integrated circuit that communicates with a module that is not dynamically reconfigurable via the port. First circuitry of the DRM and circuitry external to the DRM are implemented. The first circuitry connects to the circuitry external to the DRM via the port. The circuitry external to the DRM is within the module that is not dynamically reconfigurable. The method further includes locking routing resources connecting the circuitry external to the DRM to a location associated with a boundary of the DRM for the port; and implementing second circuitry of the DRM by reusing the locked routing resources. The second circuitry is routed to connect to the location associated with the boundary of the DRM for the port.

Generating a module interface for partial reconfiguration design flows

A system and method are provided for verifying implementation of a logic core in a complete bitstream. A logic core bitstream is extracted from the complete bitstream. The logic core bitstream is compared to a reference bitstream of the logic core for a target device. In response to no discrepancy in the comparison of the logic core bitstream and the reference bitstream, a data value is stored indicating that the logic core implementation contained in the complete bitstream is verified.

Verification of logic core implementation

A method of processing a logical netlist for implementing a circuit design within a programmable logic device includes identifying a dynamically reconfigurable module (DRM) including at least one port from the logical netlist and determining whether the port connects with function logic for a function of the DRM. If the port connects with function logic, logic is inferred that connects the function logic with logic that is external to the DRM. If the port does not connect with function logic, logic is inferred that connects the port of the DRM with logic that is external to the DRM according to an attribute associated with the port. The logical netlist is updated to specify the inferred logic.

A method of managing correlation data for a design implementation process can include identifying correlation data from each of a plurality of design applications. Each of the design applications can generate a circuit description and the correlation data can specify associations between circuit elements of different ones of the circuit descriptions. The method also can include storing the circuit descriptions and the correlation data independently of one another and determining a relationship among circuit elements of the circuit descriptions according to the correlation data.

Design independent correlation data storage for use with physical design of programmable logic devices

A method of implementing a circuit design can include selecting the circuit design to be implemented, wherein the circuit design comprises a plurality of partitions, and receiving a user input specifying a value of a partition property. The partition property can be associated with a selected one of the plurality of partitions of the circuit design. The method also can include performing an incremental implementation flow upon the circuit design for implementation by, at least in part, selectively modifying portions of a prior implementation of the selected partition in accordance with the value of the partition property.

Method and apparatus for circuit design closure using partitions

Method and apparatus for module design in a PLD is described. In one example, a PLD includes a reconfigurable module, a static module, and at least one logic interface macro. The reconfigurable module includes a signal interface and is configured for active partial reconfiguration. The static module includes a signal interface. Each logic interface macro includes first pins coupled to the signal interface of the reconfigurable module and second pins coupled to the signal interface of the static module. The first pins and the second pins are disposed in an implementation area of the reconfigurable module. In one embodiment, each logic interface macro includes a slice of a configurable logic block (CLB). In some embodiments, each logic interface macro is implemented using another type of logic block, such as a block RAM and/or multiplier block.

Versatile bus interface macro for dynamically reconfigurable designs

A method of managing an incremental implementation flow (incremental flow) for a circuit design can include storing dependency management data for the incremental flow for the circuit design and, from a first application, invoking at least one plug-in software component configured to access the dependency management data for the circuit design. The method further can include identifying partitions of the circuit design that must be run during the incremental flow using the plug-in software component.

Plug-in component-based dependency management for partitions within an incremental implementation flow

A method of incremental flow for a programmable logic device can include identifying elements of a hardware description language representation of a circuit design and specifying a hierarchy of partitions for selected ones of the elements. Portions of implementation data from a prior implementation flow for the circuit design can be associated with corresponding partitions. Selected portions of the implementation data from the prior implementation flow for at least one partition can be re-used during an incremental flow of the circuit design.

Partition-based incremental implementation flow for use with a programmable logic device

Method and apparatus for implementing a pre-implemented circuit design for a programmable logic device is described. In one example, a definition of the pre-implemented circuit design is obtained (). The definition includes a first physical implementation and a first logical implementation. A second logical implementation is produced () for an instance of the pre-implemented circuit design using the first logical implementation. A second physical implementation is produced () for then instance of the pre-implemented circuit design using the first physical implementation.

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Longmont, CO, United States of America

W Story Leavesley, Iii