Freescale Semiconductor,inc.

International Business Machines Corporation

Chartered Semiconductor Manufacturing Ltd (corporation)

Other

Samsung Electronics Co., Ltd.

Globalfoundries Inc.

Infineon Technologies North America Corp.

Paul Scherrer Institut

Garching Innovations Gmbh

Voon-Yew Thean

Bich-Yen Nguyen

Mariam G Sadaka

Ted R White

Alexander L Barr

Da Zhang

Victor H Vartanian

Leo Mathew

Weipeng Li

Marius K Orlowski

Shawn George Thomas

Tab Allen Stephens

Dina H Triyoso

Yang Du

Brian J Goolsby

Xiangdong Chen

Chun-Li Liu

Brian A Winstead

Young Way Teh

Dejan Jovanovic

Jian Feng Chen

Dae-Gyu Park

Olubunmi O Adetutu

Kenneth Jay Stein

Jae-Eun Park

Venkat Kolagunta

Konstantin V Loiko

Gregory S Spencer

Zhonghai Shi

Deleep R Nair

Marc A Rossow

Melissa O Zavala

Linda B McCormick

Colita M Parker

Haizhou Yin

Sinan Goktepeli

Dong-Hun Lee

Philip J Tobin

Srikanth Balaji Samavedam

Alexander Barr

Jin-Ping Han

Yong Meng Lee

Vishal P Trivedi

Paul Grudowski

Anda C Mocuta

Thien T Nguyen

Laegu Kang

M Dean Sciacca

Christopher V Baiocco

Jin Zheng Wallner

Melanie J Sherony

Hsing H Tseng

Sriram Kalpat

Stefan Zollner

Matthew W Stoker

Veeraraghavan Dhandapani

Yasuhito Shiho

Veer Dhandapani

Jing Liu

Darren V Goedeke

Ava Wan

Yong-Meng Lee

Franck Arnaud

Jie Chen

Jong Ho Lee

Qianghua Xie

Detlev Gruetzmacher

Lubomir Cergel

Shawn G Thomas

Peter Wennekers

Andreas A Wild

Oliver G Schmidt

The present disclosure provides a method of forming an electrical device. The method may begin with forming a gate structure on a substrate, in which a spacer is present in direct contact with a sidewall of the gate structure. A source region and a drain region is formed in the substrate. A metal semiconductor alloy is formed on the gate structure, an outer sidewall of the spacer and one of the source region and the drain region. An interlevel dielectric layer is formed over the metal semiconductor alloy. A via is formed through the interlevel dielectric stopping on the metal semiconductor alloy. An interconnect is formed to the metal semiconductor alloy in the via. The present disclosure also includes the structure produced by the method described above.

Spacer protection and electrical connection for array device

A semiconductor device is formed in a semiconductor layer. A gate stack is formed over the semiconductor layer and comprises a first conductive layer and a second layer over the first layer. The first layer is more conductive and provides more stopping power to an implant than the second layer. A species is implanted into the second layer. Source/drain regions are formed in the semiconductor layer on opposing sides of the gate stack. The gate stack is heated after the step of implanting to cause the gate stack to exert stress in the semiconductor layer in a region under the gate stack.

Method of forming a semiconductor device featuring a gate stressor and semiconductor device

Solutions for forming an integrated circuit structure having a substantially planar N-P step height are disclosed. In one embodiment, a method includes: providing a structure having an n-type field effect transistor (NFET) region and a p-type field effect transistor (PFET) region; forming a mask over the PFET region to leave the NFET region exposed; performing dilute hydrogen-flouride (DHF) cleaning on the exposed NFET region to substantially lower an STI profile of the NFET region; and forming a silicon germanium (SiGE) channel in the PFET region after the performing of the DHF.

Integrated circuit structure having substantially planar N-P step height and methods of forming

An integrated circuit structure includes a substrate and at least one pair of complementary transistors on or in the substrate. The pair of complementary transistors comprises a first transistor and a second transistor. The structure also includes a first stress-producing layer on the first transistor and the second transistor, and a second stress-producing layer on the first stress-producing layer over the first transistor and the second transistor. The first stress-producing layer applies tensile strain force on the first transistor and the second transistor. The second stress-producing layer applies compressive strain force on the first stress-producing layer, the first transistor, and the second transistor.

Balancing NFET and PFET performance using straining layers

A semiconductor fabrication process includes masking a first region, e.g., an NMOS region, of a semiconductor wafer, e.g., a biaxial, tensile strained silicon on insulator (SOI) wafer and creating recesses in source/drain regions of a second wafer region, e.g., a PMOS region. The wafer is then annealed in an ambient that promotes migration of silicon. The source/drain recesses are filled with source/drain structures, e.g., by epitaxial growth. The anneal ambient may include a hydrogen bearing species, e.g., Hor GeH, maintained at a temperature in the range of approximately 800 to 1000&#xb0; C. The second region may be silicon and the source/drain structures may be silicon germanium. Creating the recesses may include creating shallow recesses with a first etch process, performing an amorphizing implant to create an amorphous layer, performing an inert ambient anneal to recrystallize the amorphous layer, and deepening the shallow recesses with a second etch process.

Selective uniaxial stress modification for use with strained silicon on insulator integrated circuit

A semiconductor process and apparatus includes forming NMOS and PMOS transistors () with enhanced hole mobility in the channel region of a transistor by selectively relaxing part of a biaxial-tensile strained semiconductor layer () in a PMOS device area () to form a relaxed semiconductor layer (), and then epitaxially growing a bi-axially stressed silicon germanium channel region layer () prior to forming the NMOS and PMOS gate structures () overlying the channel regions, and then depositing a contact etch stop layer (-) over the NMOS and PMOS gate structures. Embedded silicon germanium source/drain regions () may also be formed adjacent to the PMOS gate structure () to provide an additional uni-axial stress to the bi-axially stressed channel region.

CMOS process with optimized PMOS and NMOS transistor devices

A semiconductor device () is formed in a semiconductor layer (). A gate stack () is formed over the semiconductor layer and comprises a first conductive layer () and a second layer () over the first layer. The first layer is more conductive and provides more stopping power to an implant than the second layer. A species () is implanted into the second layer. Source/drain regions () are formed in the semiconductor layer on opposing sides of the gate stack. The gate stack is heated after the step of implanting to cause the gate stack to exert stress in the semiconductor layer in a region under the gate stack.

A semiconductor device is provided which comprises a semiconductor layer (), a dielectric layer (), first and second gate electrodes () having first and second respective work functions associated therewith, and a layer of hafnium oxide () disposed between said dielectric layer and said first and second gate electrodes.

Semiconductor device with selectively modulated gate work function

A semiconductor process and apparatus includes forming &#x3c;100&#x3e; channel orientation CMOS transistors () with enhanced hole mobility in the NMOS channel region and reduced channel defectivity in the PMOS region by depositing a first tensile etch stop layer () over the PMOS and NMOS gate structures, etching the tensile etch stop layer () to form tensile sidewall spacers () on the exposed gate sidewalls, and then depositing a second hydrogen rich compressive or neutral etch stop layer () over the NMOS and PMOS gate structures () and the tensile sidewall spacers (). In other embodiments, a first hydrogen-rich etch stop layer () is deposited and etched to form sidewall spacers () on the exposed gate sidewalls, and then a second tensile etch stop layer () is deposited over the NMOS and PMOS gate structures () and the sidewall spacers ().

Method for transistor fabrication with optimized performance

Disclosed are embodiments of a p-type, silicon germanium (SiGe), high-k dielectric-metal gate, metal oxide semiconductor field effect transistor (PFET) having an optimal threshold voltage (Vt), a complementary metal oxide semiconductor (CMOS) device that includes the PFET and methods of forming both the PFET alone and the CMOS device. The embodiments incorporate negatively charged ions (e.g., fluorine (F), chlorine (Cl), bromine (Br), iodine (I), etc.) into the high-k gate dielectric material of the PFET only so as to selectively adjust the negative Vt of the PFET (i.e., so as to reduce the negative Vt of the PFET).

Method to reduce threshold voltage (Vt) in silicon germanium (SiGe), high-k dielectric-metal gate, p-type metal oxide semiconductor field effect transistors

An electronic device can include a first semiconductor portion and a second semiconductor portion, wherein the compositions of the first and second semiconductor portions are different from each other. In one embodiment, the first and second semiconductor portions can have different stresses compared to each other. In one embodiment, the electronic device may be formed by forming an oxidation mask over the first semiconductor portion. A second semiconductor layer can be formed over the second semiconductor portion of the first semiconductor layer and have a different composition compared to the first semiconductor layer. An oxidation can be performed, and a concentration of a semiconductor element (e.g., germanium) within the second portion of the first semiconductor layer can be increased. In another embodiment, a selective condensation may be performed, and a field isolation region can be formed between the first and second portions of the first semiconductor layer.

Electronic devices including a semiconductor layer

A wafer having a silicon layer that is strained is used to form transistors. The silicon layer is formed by first forming a silicon germanium (SiGe) layer of at least 30 percent germanium that has relaxed strain on a donor wafer. A thin silicon layer is epitaxially grown to have tensile strain on the relaxed SiGe layer. The amount tensile strain is related to the germanium concentration. A high temperature oxide (HTO) layer is formed on the thin silicon layer by reacting dichlorosilane and nitrous oxide at a temperature of preferably between 800 and 850 degrees Celsius. A handle wafer is provided with a supporting substrate and an oxide layer that is then bonded to the HTO layer. The HTO layer, being high density, is able to hold the tensile strain of the thin silicon layer. The relaxed SiGe layer is cleaved then etched away to expose the thin silicon layer. A low temperature silicon layer is then epitaxially grown with tensile strain, correlated to the tensile strain of the thin silicon layer, on the thin silicon layer using trisilane at a temperature preferably not in excess of 500 degrees Celsius. The resulting tensile strain, correlated to the strain of the thin silicon layer, is thus also correlated to the germanium concentration of the relaxed SiGe layer. The thickness of the low temperature silicon layer, using the trisilane at low temperature, is significantly greater than what would normally be expected for a silicon layer of that tensile strain.

Method for forming a semiconductor structure having a strained silicon layer

A semiconductor process and apparatus provide a dual or hybrid substrate by forming a second semiconductor layer () that is isolated from, and crystallographically rotated with respect to, an underlying first semiconductor layer () by a buried insulator layer (); forming an STI region () in the second semiconductor layer () and buried insulator layer (); exposing the first semiconductor layer () in a first area () of a STI region (); epitaxially growing a first epitaxial semiconductor layer () from the exposed first semiconductor layer (); and selectively etching the first epitaxial semiconductor layer () and the second semiconductor layer () to form CMOS FinFET channel regions (e.g.,) and planar channel regions (e.g.,) from the first epitaxial semiconductor layer () and the second semiconductor layer ().

Twisted dual-substrate orientation (DSO) substrates

An integrated circuit includes NMOS and PMOS transistors. The NMOS has a strained channel having first and second stress values along first and second axes respectively. The PMOS has a strained channel having third and fourth stress values along the first and second axes. The first value stress differs from the third value and the second value differs from the fourth value. The NMOS and PMOS have a common length (L) and effective width (W), but differ in length of diffusion (SA) and/or width of source/drain (WS). The NMOS WS may exceed the PMOS WS. The NMOS may include multiple dielectric structures in the active layer underlying the gate. The SA of the PMOS may be less than the SA of the NMOS. The integrated circuit may include a tensile stressor of silicon nitride over the NMOS and a compressive stressor of silicon nitride over the PMOS.

Selective uniaxial stress relaxation by layout optimization in strained silicon on insulator integrated circuit

Two different transistors types are made on different crystal orientations in which both are formed on SOI. A substrate has an underlying semiconductor layer of one of the crystal orientations and an overlying layer of the other crystal orientation. The underlying layer has a portion exposed on which is epitaxially grown an oxygen-doped semiconductor layer that maintains the crystalline structure of the underlying semiconductor layer. A semiconductor layer is then epitaxially grown on the oxygen-doped semiconductor layer. An oxidation step at elevated temperatures causes the oxide-doped region to separate into oxide and semiconductor regions. The oxide region is then used as an insulation layer in an SOI structure and the overlying semiconductor layer that is left is of the same crystal orientation as the underlying semiconductor layer. Transistors of the different types are formed on the different resulting crystal orientations.

Semiconductor device structure

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