Semiconductor Components Industries, LLC

Cypress Semiconductor Corporation

Tower Semiconductor Ltd.

On Semiconductor Trading, Ltd.

Parade Technologies, Ltd.

Vladimir Korobov

Swarnal Borthakur

Marc Allen Sulfridge

Oliver Pohland

Jaroslav Hynecek

Robert Michael Guidash

Jeong Soo Byun

Sergey Velichko

Eric Gordon Stevens

David Cohen

John W Ladd

Clifford I Drowley

Assaf Lahav

Alexandre Gourevitch

Bartosz Piotr Banachowicz

Peter G Vavaroutsos

Muhammad Maksudur Rahman

Anatoly Sergienko

Shai Kfir

Daniel Tekleab

Naor Inbar

Sylvie Rockman

Miriam Grossman

Implementations of image sensors may include: a first die including a plurality of detectors adapted to convert photons to electrons; a second die including a plurality of transistors, passive electrical components, or both transistors and passive electrical components; a third die including analog circuitry, logic circuitry, or analog and logic circuitry. The first die may be hybrid bonded to the second die, and the second die may be fusion bonded to the third die. The plurality of transistors, passive electrical components, or transistors and passive electrical components of the second die may be adapted to enable operation of the plurality of detectors of the first die. The analog circuitry, logic circuitry, and analog circuitry and logical circuitry may be adapted to perform signal routing.

Die stacked image sensors and related methods

An imaging system may include an image sensor package with through-oxide via connections between the image sensor die and the digital signal processing die in the image sensor package. The image sensor die and the digital signal processing die may be attached to each other. The through-oxide via may connect a bond pad on the image sensor die with metal routing paths in the image sensor and digital signal processing dies. The through-oxide via may simultaneously couple the image sensor die to the digital signal processing die. The through-oxide via may be formed through a shallow trench isolation structure in the image sensor die. The through-oxide via may be formed through selective etching of the image sensor and digital signal processing dies.

Imaging systems with through-oxide via connections

An imaging pixel may have a fully depleted charge transfer path between a pinned photodiode and a floating diffusion region. A pinned transfer diode may be coupled between the pinned photodiode and the floating diffusion region. The imaging pixel may be formed in upper and lower substrates with an interconnect layer coupling the upper substrate to the lower substrate. The imaging pixel may include one or more storage diodes coupled between the transfer diode and the floating diffusion region. The imaging pixel may be used to capture high dynamic range images with flicker mitigation, images synchronized with light sources, or for high frame rate operation.

Imaging pixels with a fully depleted charge transfer path

Electronic devices may include High Dynamic Range (HDR) complementary metal-oxide-semiconductor (CMOS) image sensor arrays that are illuminated from the back side of the substrate and operate in a rolling shutter (RS) scanning mode. An image sensor may include stacked chips to improve image sensor performance. For example, by stacking photodiodes on top of each other and using dichroic dielectric layers in chip-to-chip isolation, sensor sensitivity may be increased, Moir&#xe9; effect may be reduced, and the overall image sensor performance may be improved. Image sensors may include a charge sensing and charge storing scheme where charge generated by low incident light levels is transferred onto a charge sensing node of an in-pixel inverting feedback amplifier and charge generated by high incident light levels overflows a certain potential barrier built in the pixel, is stored on capacitors, and is sensed by a source follower.

Image sensors with stacked photodiodes

An image sensor may include a symmetrical imaging pixel with a floating diffusion region. The floating diffusion region may be formed in the center of the imaging pixel. A shallow p-well may be formed around the floating diffusion region. A transfer gate configured to transfer charge from a photodiode to the floating diffusion region may be ring-shaped with an opening that overlaps the floating diffusion region. Isolation regions including deep trench isolation and a p-well may surround the photodiode of the imaging pixel. A p-stripe may couple the shallow p-well around the floating diffusion region to the isolation regions. The floating diffusion regions of neighboring pixels may be coupled together with additional conductive layers to implement shared configurations.

Imaging sensor having floating region of imaging device on one substrate electrically coupled to another floating region formed on a second substrate

An image sensor pixel may include a photodiode, a floating diffusion, and a transfer gate. A buried channel may be formed under the transfer gate. The buried channel may extend from the floating diffusion to overlap a portion of the transfer gate without extending completely beneath the transfer gate or reaching the photodiode. The buried channel may provide a path for antiblooming current from the photodiode to reach the floating diffusion, while allowing for the transfer gate off voltage to remain high enough to prevent transfer gate dark current from flowing into the photodiode.

Apparatus and methods for buried channel transfer gate

In one form, a hybrid bonded image sensor comprises a photodiode chip, a circuit carrying chip, and an interconnection. The photodiode chip provides charge to a first floating diffusion in response to incident light, wherein the first floating diffusion is coupled to a first terminal on a first surface of the photodiode chip. The circuit carrying chip has a first terminal aligned with the first terminal of the photodiode chip, the circuit carrying chip forming an output voltage based on charge transferred on the first floating diffusion sensed from the first terminal thereof. The interconnection connects the first terminal of the photodiode chip to the first terminal of the circuit carrying chip.

Hybrid bonded image sensor and method of operating such image sensor

An image sensor. Implementations may include: a first die including a plurality of pixels; a second die including a plurality of transistors, capacitors, or both transistors and capacitors; a third die including analog circuitry, logic circuitry, or analog and logic circuitry. The first die may be hybrid bonded to the second die, and the second die may be fusion bonded to the third die. The plurality of transistors, capacitors or transistors and capacitors of the second die may be adapted to enable operation of the plurality of pixels of the first die. The analog circuitry, logic circuitry, and analog circuitry and logical circuitry may be adapted to perform signal routing.

An image sensor may have control circuitry and an array of pixels having corresponding photodiodes. The pixels may be arranged into groups. Photodiodes in each of the groups may share a common charge storage region. Each photodiode has an associated sensitivity provided by a corresponding color filter element. The control circuitry may perform multiple charge transfer operations to transfer charge accumulated in high sensitivity photodiodes in the group to the shared charge storage region, may readout image signals corresponding to the transferred charge, and may combine the image signals to generate final image signals for the photodiodes. The control circuitry may transfer charge accumulated in low sensitivity photodiodes in the group to the shared charge storage region after the image signals generated by the high sensitivity photodiodes have been read out, thereby increasing the maximum signal to noise ratio of the low sensitivity photodiodes without causing charge blooming.

Systems and methods for operating image sensor pixels having different sensitivities and shared charge storage regions

An image sensor may be provided with an array of image pixels formed on a substrate having front and back surfaces. Each pixel may have a photodiode that receives light through the back surface, a floating diffusion node, and a charge transfer gate. The floating diffusion node may be formed in the center of the photodiode and may be surrounded by the charge transfer gate at the front surface. The charge transfer gate may isolate the floating diffusion node from the surrounding photodiode. The pixel may include reset transistor gates, an addressing transistor gate, and a source follower transistor arranged about the periphery of the photodiode. By centering the floating diffusion node and charge transfer gate within the photodiode, the image pixels may have improved shutter efficiency and charge transfer efficiency relative to pixels having floating diffusion nodes at non-centralized locations.

Global shutter image sensor pixels having centralized charge storage regions

An embodiment of a capacitive sensor array may comprise a first set of sensor electrodes each comprising one or more large subelements and a second set of sensor electrodes each comprising one or more small subelements. In one embodiment, each of the small subelements may be smaller than any of the large subelements, and the first set of sensor electrodes and the second set of sensor electrodes are formed from a single layer of conductive material. In one embodiment, the surface area of the capacitive sensor array may be divisible into a grid of N&#xd7;M unit cells, wherein each of the N&#xd7;M unit cells contains one of the large subelements and k of the small subelements, where k is greater than or equal to 2.

Single layer sensor pattern

A method and apparatus for a reverse metal-insulator-metal (MIM) capacitor. The apparatus includes a lower metal layer, a bottom electrode, and an upper metal layer. The lower metal layer is disposed above a substrate layer. The bottom electrode is disposed above the lower metal layer and coupled to the lower metal layer. The upper metal layer is disposed above the bottom electrode. The upper metal layer comprises a top electrode of a metal-insulator-metal (MIM) capacitor.

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San Mateo, CA, United States of America

Vladimir Korobov