Texas Instruments Corporation

Vivian Liu

Freidoon Mehrad

Amitava Chatterjee

Jiong-Ping Lu

Scott David Johnson

Lindsey H Hall

Clint Montgomery

The present invention substantially removes dry etch residue from a dry plasma etch processprior to depositing a cobalt layeron silicon substrate and/or polysilicon material. Subsequently, one or more annealing processesare performed that cause the cobalt to react with the silicon thereby forming cobalt silicide regions. The lack of dry etch residue remaining between the deposited cobalt and the underlying silicon permits the cobalt silicide regions to be formed substantially uniform with a desired silicide sheet and contact resistance. The dry etch residue is substantially removed by performing a first cleaning operationand then an extended cleaning operationthat includes a suitable cleaning solution. The first cleaning operation typically removes some, but not all of the dry etch residue. The extended cleaning operationis performed at a higher temperature and/or for an extended duration and substantially removes dry etch residue remaining after the first cleaning operation

Process method to facilitate silicidation

The present invention pertains to a multi-layer sidewall process () that facilitates forming a transistor in a manner that allows adherence to certain design rules while concurrently mitigating adverse effects associated with forming areas of transistors close to one another. First sidewall spacers having first widths are formed () alongside a gate structure of a transistor to facilitate implanting source/drain dopants far enough away from the gate structure so that dopant atoms are unlikely to migrate into a channel area under the gate structure. Additionally, the process provides uniform layers for dopant atoms to pass through to mitigate variations in device characteristics across a wafer. The manner of forming the sidewall spacers also allows a salicide blocking process to be simplified. The first sidewall spacers are subsequently reduced () to establish second sidewall spacers having second widths which are smaller than the first widths. The smaller second sidewall spacers facilitate compliance with design rules by allowing source and drain contacts to be formed closer to the gate structure.

Multi-layer reducible sidewall process

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Garland, TX, United States of America

Vivian Liu