Micron Technology Incorporated

Nan Ya Technology Corporation

Intel Corporation

Vishwanath Bhat

Chris M Carlson

Vassil N Antonov

Noel Rocklein

F Daniel Gealy

Farrell Martin Good

Tsai-Yu Huang

Kevin R Shea

Rishikesh Krishnan

Irina V Vasilyeva

Dan Gealy

Bhaskar Srinivasan

Cancheepuram V Srividya

Chun-I Hsieh

Kyle B Campbell

Kyuchul Chong

John A Smythe

Prashant Raghu

Nik Mirin

M Noel Rocklein

Dave Peterson

Cunyu Yang

Praveen Vaidyanathan

Jeff Hull

Matthew N Rocklein

Joseph Neil Greeley

Niraj B Rana

Brett W Busch

Daniel Gealy

Duane M Goodner

Jennifer K Sigman

Shyam Surthi

Qian Tao

Zhe Song

Gordon Morrison

Chun I Hsieh

Wei Hui Hsu

Jeff Hall

Kotha Sai Madhukar Reddy

A method of forming a semiconductor structure. The method comprises forming a protective portion of a liner on at least a portion of stack structures on a substrate. The protective portion comprises a material formulated to adhere to the stack structures. A conformal portion of the liner is formed on the protective portion of the liner or on the protective portion of the liner and exposed materials of the stack structures. At least one of the protective portion and the conformal portion does not comprise aluminum. Additional methods of forming a semiconductor structure are disclosed, as are semiconductor structures including the liners comprising the protective portion and the conformal portion.

Methods of forming devices including multi-portion liners

Devices including multi-portion liners

Methods of forming semiconductor structures including multi-portion liners

Semiconductor structures including multi-portion liners

Some embodiments include methods of forming rutile-type titanium oxide. A monolayer of titanium nitride may be formed. The monolayer of titanium nitride may then be oxidized at a temperature less than or equal to about 550&#xb0; C. to convert it into a monolayer of rutile-type titanium oxide. Some embodiments include methods of forming capacitors that have rutile-type titanium oxide dielectric, and that have at least one electrode comprising titanium nitride. Some embodiments include thermally conductive stacks that contain titanium nitride and rutile-type titanium oxide, and some embodiments include methods of forming such stacks.

Constructions comprising rutile-type titanium oxide; and methods of forming and utilizing rutile-type titanium oxide

A method of forming a capacitor includes depositing a dielectric metal oxide layer of a first phase to a thickness no greater than 75 Angstroms over an inner conductive capacitor electrode material. The first phase dielectric metal oxide layer has a k of at least 15. Conductive RuOis deposited over and into physical contact with the dielectric metal oxide layer. Then, the RuOand the dielectric metal oxide layer are annealed at a temperature below 500&#xb0; C. The RuOin physical contact with the dielectric metal oxide during the annealing facilitates a change of the dielectric metal oxide layer from the first phase to a second crystalline phase having a higher k than the first phase. The annealed dielectric metal oxide layer is incorporated into a capacitor dielectric region of a capacitor construction. Other implementations are disclosed.

Methods of forming capacitors

Graded dielectric layers and methods of fabricating such dielectric layers provide dielectrics in a variety of electronic structures for use in a wide range of electronic devices and systems. In an embodiment, a dielectric layer is graded with respect to a doping profile across the dielectric layer. In an embodiment, a dielectric layer is graded with respect to a crystalline structure profile across the dielectric layer. In an embodiment, a dielectric layer is formed by atomic layer deposition incorporating sequencing techniques to generate a doped dielectric material.

Graded dielectric structures

A semiconductor structure may include a first electrode over a substrate, a high-K dielectric material over the first electrode, and a second electrode over the high-K dielectric material, wherein at least one of the first electrode and the second electrode may include a material selected from the group consisting of a molybdenum nitride (MoN) material, a molybdenum oxynitride (MoON) material, a molybdenum oxide (MoO) material, and a molybdenum-based alloy material comprising molybdenum and nitrogen.

Semiconductor structures including molybdenum nitride, molybdenum oxynitride or molybdenum-based alloy material, and method of making such structures

Embodiments of the present disclosure describe a liner for a phase change memory (PCM) array and associated techniques and configurations. In an embodiment, a substrate, an array of phase change memory (PCM) elements disposed on the substrate, wherein individual PCM elements of the array of PCM elements comprise a chalcogenide material and a liner disposed on sidewall surfaces of the individual PCM elements, wherein the liner comprises aluminum (Al), silicon (Si) and oxygen (O). Other embodiments may be described and/or claimed.

Liner for phase change memory (PCM) array and associated techniques and configurations

Some embodiments include a method of forming a capacitor. An opening is formed through a silicon-containing mass to a base, and sidewalls of the opening are lined with protective material. A first capacitor electrode is formed within the opening and has sidewalls along the protective material. At least some of the silicon-containing mass is removed with an etch. The protective material protects the first capacitor electrode from being removed by the etch. A second capacitor electrode is formed along the sidewalls of the first capacitor electrode, and is spaced from the first capacitor electrode by capacitor dielectric. Some embodiments include multi-material structures having one or more of aluminum nitride, molybdenum nitride, niobium nitride, niobium oxide, silicon dioxide, tantalum nitride and tantalum oxide. Some embodiments include semiconductor constructions.

Multi-material structures and capacitor-containing semiconductor constructions

Constructions comprising thermally conductive stacks containing rutile-type titanium oxide

A method for fabricating a capacitor includes: (1) forming a bottom electrode on a substrate; (2) forming a template layer on the bottom electrode; (3) performing a plurality of atomic layer deposition (ALD) cycles by using water vapor as an oxidant thereby depositing a first TiO2 layer on the template layer; and (4) performing ozone pulse and purge step to transform entire thickness of the first TiO2 layer into rutile phase.

Method for fabricating capacitor having rutile titanium oxide dielectric film

Methods of forming a capacitor including forming a titanium nitride material within at least one aperture defined by a support material, forming a ruthenium material within the at least one aperture over the titanium nitride material, and forming a first conductive material over the ruthenium material within the at least one aperture. The titanium nitride material may be oxidized to a titanium dioxide material. A second conductive material may be formed over a surface of the titanium dioxide material. A semiconductor device may include at least one capacitor, wherein a major longitudinal portion of the at least one capacitor is not surrounded by a solid material. The capacitor may include a first electrode; a ruthenium oxide material laterally adjacent the first electrode; a rutile titanium dioxide material laterally adjacent the ruthenium oxide material; and a second electrode laterally adjacent the rutile titanium dioxide material.

Methods of forming capacitors and semiconductor devices including a rutile titanium dioxide material

Growing community of inventors

Boise, ID, United States of America

Vishwanath Bhat