Siemens Aktiengesellschaft

International Business Machines Corporation

Virinder S Grewal

Volker B Laux

John C Forster

Dragan Valentin Podlesnik

Donna Rizzone Cote

Anthony J Konecni

Chi-Hua Yang

Contact holes through a dielectric are formed by forming a layer of polysilicon having a thickness between 0.02 um and 0.15 um inclusive on the dielectric, forming a layer of resist having a thickness between 0.4 um and 0.6 um inclusive on the layer of polysilicon, making a mask of the layer of resist, using it to form a mask in the layer of polysilicon and etching contact holes in the dielectric by exposing it to etching gasses through the apertures in the polysilicon mask. When the dielectric includes a layer of oxide adjacent the polysilicon mask and a layer of nitride between it and elements of the device, the resist mask is removed prior to etching the contact hole and a gas mixture of: C.sub.4 F.sub.8 ; one of Ar, H, F; CO; CF.sub.4 or C.sub.2 F.sub.6 is used. Contact holes are made through a dielectric to conductors in a substrate by the same method, and desired cross sections are obtained by using a second resist mask and a selective etch for the polysilicon followed by a selective etch for the dielectric. These structures can be stacked and suitable interconnections made by the described method. Contact holes to gate electrodes can be etched using the basic process.

Etching high aspect contact holes in solid state devices

In a PECVD process, the plasma potential is controlled and maintained at a uniform level to confine the formed plasma to the gap area between the electrodes away from the influence of the walls of the discharge chamber. The plasma potential is controlled by operating the system at a high pressure, above about 12 Torr, and monitoring the operation by observing the DC bias on the upper or driven electrode until a positive potential, preferably greater than about 10V, is developed. At this point a symmetrical glow discharge and a controlled plasma exists between the driven electrode and the susceptor electrode, controllable by maintaining the pressure between about 14 and 20 Torr, to reduce plasma damage to the semiconductor body being coated which maximizes yield.

Process for reducing circuit damage during PECVD in single wafer PECVD

An etch chamber for anisotropic and selective etching of a semiconductor wafer contains a dielectric window and an externally located first electrode member adjacent to the dielectric window for generating a plasma within the chamber. A second electrode member is located within the chamber for exciting the plasma generated by the first electrode member. A third electrode is located between the first electrode member and the dielectric window for sputtering the dielectric window to provide sidewall passivation for anisotropic and selective etching of a semiconductor wafer located within said chamber. Each electrode member is powered by its own separate RF generator. This arrangement enables the independent control of each of the three electrode members to optimize the etching of the semiconductor wafer located within the chamber.

Etch chamber having three independently controlled electrodes

A method of plasma etching a gate stack on silicon with a chlorine-containing plasma precursor gas in a vacuum chamber fitted with an electrically conductive planar coil disposed outside the chamber and adjacent to a dielectric window mounted in a wall of the chamber, the conductive planar coil coupled to a first radiofrequency source that matches the impedance of the source to the coil, and a second radiofrequency source coupled to a substrate support mounted in the chamber in a direction parallel to the planar coil which comprises limiting the power during etching to 0-200 watts from the first radiofrequency source and to 50-200 watts from the second radiofrequency source. The resultant etch is anisotropic, and avoids charging of the substrate to be etched. When the gate stack comprises conductive polysilicon, the preferred plasma precursor etch gas is a mixture of hydrogen chloride and chlorine, when a highly selective etch is obtained.

Plasma etching method

A method for fabricating a stacked gate array on a semiconductor wafer. The method comprises the steps of providing a reaction chamber having an upper inductive coil and a lower capacitive electrode. The upper inductive coil is adjusted to a relatively low power setting of substantially less than 300 watts. The wafer is placed into the reaction chamber and plasma etched to provide the stacked gate array.

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Fishkill, NY, United States of America

Virinder S Grewal