Cree Gmbh

Monolithic Power Systems, Inc.

Maxim Integrated Products, Inc.

Alpha and Omega Semiconductor (cayman) Ltd.

Wolfspeed, Inc.

Semiq Incorporated

Logisic Devices, Inc.

Vipindas Pala

Lin Cheng

Anant Kumar Agarwal

John Williams Palmour

Edward Robert Van Brunt

Daniel Jenner Lichtenwalner

Alexander V Suvorov

Marco A Zuniga

Vijay Parthasarathy

Sudarsan Uppili

Qingchun Zhang

John Xia

Madhur Bobde

Jason Patrick Henning

Badredin Fatemizadeh

Rahul R Potera

Tony Witt

David Sheridan

Sundarsan Uppili

A method of fabricating a wide bandgap device includes providing a thin native substrate. An epitaxial layer is grown on a surface of the native substrate. After growing the epitaxial layer, a handle substrate is attached to the opposite surface of the native substrate by way of an interface layer. With the handle substrate providing mechanical support, wide bandgap devices are fabricated in the epitaxial layer using a low-temperature fabrication process. The handle substrate is detached from the native substrate after fabrication of the wide bandgap devices.

Thin wafer process for improved crystal utilization of wide bandgap devices

Junction field effect transistors (JFETs) and related manufacturing methods are disclosed herein. A disclosed JFET includes a vertical channel region located in a mesa and a first channel control region located on a first side of the mesa. The first channel control region is at least one of a gate region and a first base region. The JEFT also includes a second base region located on a second side of the mesa and extending through the mesa to contact the vertical channel region. The vertical channel can be an implanted vertical channel. The vertical channel can be asymmetrically located in the mesa towards the first side of the mesa.

Single sided channel mesa power junction field effect transistor

A power metal-oxide-semiconductor field-effect transistor (MOSFET) includes a substrate, a drift layer over the substrate, and a spreading layer over the drift layer. The spreading layer includes a pair of junction implants separated by a junction gate field effect (JFET) region. A gate oxide layer is on top of the spreading layer. The gate contact is on top of the gate oxide layer. Each one of the source contacts are on a portion of the spreading layer separate from the gate oxide layer and the gate contact. The drain contact is on the surface of the substrate opposite the drift layer.

Vertical power transistor device

Junction field effect transistors (JFETs) and related manufacturing methods are disclosed herein. A disclosed JFET includes a vertical channel region located in a mesa and a first channel control region located on a first side of the mesa. The first channel control region is at least one of a gate region and a first base region. The JFET also includes a second base region located on a second side of the mesa and extending through the mesa to contact the vertical channel region. The vertical channel can be an implanted vertical channel. The vertical channel can be asymmetrically located in the mesa towards the first side of the mesa.

Semiconductor devices include a silicon carbide drift region having an upper portion and a lower portion. A first contact is on the upper portion of the drift region and a second contact is on the lower portion of the drift region. The drift region includes a superjunction structure that includes a p-n junction that is formed at an angle of between 10&#xb0; and 30&#xb0; from a plane that is normal to a top surface of the drift region. The p-n junction extends within +/&#x2212;1.5&#xb0; of a crystallographic axis of the silicon carbide material forming the drift region.

Superjunction power semiconductor devices formed via ion implantation channeling techniques and related methods

A lateral double-diffused metal-oxide-semiconductor (LDMOS) transistor including a breakdown voltage clamp includes a drain n+ region, a source n+ region, a gate, and a p-type reduced surface field (PRSF) layer including one or more bridge portions. Each of the one or more bridge portions extends below the drain n+ region in a thickness direction. Another LDMOS transistor includes a drain n+ region, a source n+ region, a gate, an n-type reduced surface field (NRSF) layer disposed between the source n+ region and the drain n+ region in a lateral direction, a PRSF layer disposed below the NRSF layer in a thickness direction orthogonal to the lateral direction, and a p-type buried layer (PBL) disposed below the PRSF layer in the thickness direction. The drain n+ region is disposed over the PBL in the thickness direction.

LDMOS transistors with breakdown voltage clamps

The present disclosure describes vertical transistor device and methods of making the same. The vertical transistor device includes substrate layer of first conductivity type, drift layer of first conductivity type formed over substrate layer, body region of second conductivity type extending vertically into drift layer from top surface of drift layer, source region of first conductivity type extending vertically from top surface of drift layer into body region, dielectric region including first and second sections formed over top surface, buried channel region of first conductivity type at least partially sandwiched between body region on first side and first and second sections of dielectric region on second side opposite to first side, gate electrode formed over dielectric region, and drain electrode formed below substrate layer. Dielectric region laterally overlaps with portion of body region. Thickness of first section is uniform and thickness of second section is greater than first section.

Vertical transistor structure with buried channel and resurf regions and method of manufacturing the same

A silicon carbide MOSFET includes first and second source regions respectively disposed in the first and second well regions. Each of the first and second source regions extends up to a top surface of the substrate. First and second channel regions of the respective first and second well regions laterally separate the first and second source regions from a JFET region by a channel length. The first and second channel regions extend up to the top surface. The first and second channel regions are each arranged in a wave-shaped pattern at the top surface of the substrate. The wave-shaped pattern extends in first and second lateral directions. In an on-state, current flows laterally from the first and second source regions to the JFET region, and then in a vertical direction down through an extended drain region to the drain region.

Silicon carbide planar MOSFET with wave-shaped channel regions

A multi-transistor device includes first and second lateral double-diffused metal-oxide-semiconductor field effect (LDMOS) transistors sharing a first p-type reduced surface field (RESURF) layer and a first drain n+ region. In certain embodiments, the first LDMOS transistor includes a first drift region, the second LDMOS transistor includes a second drift region, and the first and second drift regions are at least partially separated by the first p-type RESURF layer in a thickness direction.

Multi-transistor device including first and second LDMOS transistors having respective drift regions separated in a thickness direction by a shared RESURF layer

A method for making an integrated device that includes a plurality of planar MOSFETs, includes forming a plurality of doped body regions in an upper portion of a silicon carbide substrate composition and a plurality of doped source regions. A first contact region is formed in a first source region and a second contact region is formed in a second source region. The first and second contact regions are separated by a JFET region that is longer in one planar dimension than the other. The first and second contact regions are separated by the longer planar dimension. The JFET region is bounded on at least one side corresponding to the longer planar dimension by a source region and a body region in conductive contact with at least one contact region.

Silicon carbide MOSFET with source ballasting

Junction field effect transistors (JFETs) and related manufacturing methods are disclosed herein. A disclosed four terminal JFET includes an integrated high voltage capacitor (HVC). The JFET includes a first terminal coupled to a drain region, a second terminal coupled to the source region, a third terminal coupled to the base region, and an integrated HVC terminal coupled to an integrated HVC electrode which forms an HVC with the drain region. The JFET also includes a channel formed by a channel region. A bias on the base region fully depletes the channel of majority carriers. The channel has an unbiased concentration of majority carriers. The integrated HVC electrode is positioned relative to the channel region such that applying the bias to the integrated HVC terminal depletes the channel by at most ten percent of the unbiased concentration of majority carriers.

Junction field effect transistor with integrated high voltage capacitor

A semiconductor apparatus has a silicon carbide substrate heavily doped with the first conductivity type and a lightly doped silicon carbide drift region of the first conductivity type over the silicon carbide substrate. A first body region in the drift region is doped with second conductivity type opposite the first. A first source region in the first body region is heavily doped with the first conductivity type. A gate trench is formed in the first source region and first body region. At least one sidewall of the gate trench is parallel to a crystal plane of the silicon carbide structure having greater carrier mobility than a C-face thereof. The gate trench extends a length of the first body region and the source region to a separation region laterally adjacent to the first region wherein the separation region is in the drift region.

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Morrisville, NC, United States of America

Vipindas Pala