Northwestern University

University of Minnesota

University of Illinois

Vinod K Sangwan

Mark C Hersam

Deep M Jariwala

Tobin Jay Marks

Hyungil Kim

Weichao Xu

Hong-Sub Lee

Megan E Beck

In Soo Kim

Lincoln J Lauhon

Amit R Trivedi

Ahish Shylendra

A GHeT includes a bottom gate formed on a substrate; a first dielectric layer (DL) formed on the bottom gate; a monolayer film formed of an atomically thin material on the first DL; a bottom contact (BC) formed on part of the monolayer film; a second DL formed on the BC; a top contact (TC) formed on the second DL on top of the BC; a network of CNTs formed on the TC and the monolayer film, to define an overlap region with the monolayer film; a third DL formed on the CNT network, the monolayer film and the TC; and a top gate formed on the third DL and overlapping with the overlap region. Such GHeT design allows gate tunability of Gaussian peak position, height and width that define Gaussian transfer characteristic, thereby enabling simplified circuit architectures for various spiking neuron functions for emerging neuromorphic applications.

Tunable gaussian heterojunction transistors, fabricating methods and applications of same

One aspect of the invention relates to a method for fabricating a memtransistor comprising growing a polycrystalline monolayer film on a substrate, wherein the polycrystalline monolayer film contains grains defining a plurality of grain boundaries thereof; and forming an electrode array on the grown polycrystalline monolayer film, wherein the electrode array has a plurality of electrodes electrically coupled with the polycrystalline monolayer film such that each pair of electrodes defines a channel in the polycrystalline monolayer film therebetween.

Method for fabricating a memtransistor

A memtransistor includes a top gate electrode and a bottom gate electrode; a polycrystalline monolayer film formed of an atomically thin material disposed between the top gate electrode and the bottom gate electrode; and source and drain electrodes spatial-apart formed on the polycrystalline monolayer film to define a channel in the polycrystalline monolayer film between the source and drain electrodes. The top gate electrode and the bottom gate electrode are capacitively coupled with the channel.

Dual-gated memtransistor crossbar array, fabricating methods and applications of same

One aspect of the invention relates to a multi-terminal memtransistor. The memtransistor includes a substrate having a first surface and an opposite, second surface, a polycrystalline monolayer film formed of an atomically thin material on the first surface of the substrate, an electrode array having a plurality of electrodes spatial-apart formed on the polycrystalline monolayer film such that each pair of electrodes defines a channel in the polycrystalline monolayer film therebetween, and a gate electrode formed on the second surface of the substrate and capacitively coupled with the channel. The polycrystalline monolayer film contains grains defining a plurality of grain boundaries thereof. The multi-terminal memtransistor operates much like a neuron by performing both memory and information processing, and can be a foundational circuit element for new forms of neuromorphic computing.

Multi-terminal memtransistors and applications of the same

A self-aligned short-channel SASC electronic device includes a first semiconductor layer formed on a substrate; a first metal layer formed on a first portion of the first semiconductor layer; a first dielectric layer formed on the first metal layer and extended with a dielectric extension on a second portion of the first semiconductor layer that extends from the first portion of the first semiconductor layer, the dielectric extension defining a channel length of a channel in the first semiconductor layer; and a gate electrode formed on the substrate and capacitively coupled with the channel. The dielectric extension is conformally grown on the first semiconductor layer in a self-aligned manner. The channel length is less than about 800 nm, preferably, less than about 200 nm, more preferably, about 135 nm.

Self-aligned short-channel electronic devices and fabrication methods of same

Thermally activated memristors from solution-processed two-dimensional (2D) semiconductors, fabricating methods and applications of the same. The memristor includes a semiconductor film formed on a nanoporous membrane, and at least two electrodes spatial-apart formed on the semiconductor film and electrically coupled with the semiconductor film to define a channel in the semiconductor film between the at least two electrodes, where the channel has one or more filaments, one or more dendrite, or a combination of them formed in the semiconductor film. The underlying switching mechanism applies generally to a range of 2D semiconductors including, but not limited to, MoS, MoSe, WS, ReS, InSe, or related 2D semiconductor materials.

Thermally activated memristors, fabricating methods and applications of same

Van der Waals heterojunctions are extended to semiconducting p-type single-walled carbon nanotube (s-SWCNT) and n-type film that can be solution-processed with high spatial uniformity at the wafer scale. The resulting large-area, low-voltage p-n heterojunctions can exhibit anti-ambipolar transfer characteristics with high on/off ratios. The charge transport can be efficiently utilized in analog circuits such as frequency doublers and keying circuits that are widely used, for example, in telecommunication and wireless data transmission technologies.

System and method for anti-ambipolar heterojunctions from solution-processed semiconductors

A method of fabricating a diode includes forming a first semiconductor layer having a first portion and a second portion extending from the first portion on a substrate; forming first and second electrodes on the substrate, the first electrode extending over and being in contact with the first portion of the first semiconductor layer; forming an insulting film to cover the first electrode and the first portion of the first semiconductor layer; and forming a second semiconductor layer having a first portion and a second portion extending from the first portion on the substrate. The second portion of the second semiconductor layer overlapping with the second portion of the first semiconductor layer to define a vertically stacked heterojunction therewith. The first portion of the second semiconductor layer extending over and being in contact with the second electrode. Each of the first and second semiconductor layers includes an atomically thin semiconductor.

Gate-tunable p-n heterojunction diode, and fabrication method and application of same

In one aspect of the invention, the memristor includes a monolayer film formed of an atomically thin material, where the monolayer film has at least one grain boundary (GB), a first electrode and a second electrode electrically coupled with the monolayer film to define a memristor channel therebetween, such that the at least one GB is located in the memristor channel, and a gate electrode capacitively coupled with the memristor channel.

Gate-tunable atomically-thin memristors and methods for preparing same and applications of same

One aspect of the invention relates to a gate-tunable p-n heterojunction diode including a vertical stacked heterojunction of two ultrathin semiconductors. In one embodiment, single-layer molybdenum disulphide of an n-type semiconductor are stacked below semiconducting single-walled carbon nanotubes of a p-type semiconductor with each of them connected to a gold electrodes to form a p-n heterojunction. The electrical properties of the p-n heterojunction can be modulated by a gate voltage applied to a gate electrode and range from an insulator to a linear-response resistor to a highly rectifying diode. The gate tunability of the p-n heterojunction also allows spectral control over the photoresponse.

Growing community of inventors

Syracuse, NY, United States of America

Vinod K Sangwan