Ncr Corporation

Vinod K Dham

Edward H Honnigford

Murray L Trudel

Robert F Pfeifer

John K Stewart, Jr

A process for fabricating volatile and nonvolatile field effect devices on a common semiconductor wafer, and a unique composite structure for a nonvolatile memory device fabricated according to the process. A distinct feature of the process is the elimination of nitride from beneath any poly I layers while selectively retaining sandwiched and coextensive segments of nitride and poly II layers for the memory devices. In one form, the method commences with a wafer treated according to the general localized oxidation of silicon process, followed by a blanket enhancement implant and selectively masked depletion implants. The succeeding contact etch step is followed by a deposition of a poly I layer, a resistor forming implant and a patterned etch of the poly I layer. Thereafter, a first isolation oxide is grown, selective implants are performed to center the memory window, the memory area is etched, and the memory area is covered by a regrowth of a very thin memory oxide. The wafer is then coated with nitride and poly II, before undergoing a patterned plasma etch which successively and coextensively removes poly II and nitride in unwanted areas. Consequently, any nitride which remains is in a sandwiched arrangement with an overlying layer of poly II. The process inherently retains no nitride under any poly I layer, and thereby enhances the reliability of the complete IC. The composite nonvolatile memory device includes a poly II nonvolatile memory capacitor, a poly II depletion IGFET, and a poly I depletion IGFET over a single continuum of channel. The structural arrangement provides for selective access to the nonvolatile memory capacitor through the poly I IGFET during the write mode.

Mixed dielectric process and nonvolatile memory device fabricated thereby

A process for making buried contacts without damaging the surface of the silicon substrate while etching the pattern of a poly interconnect layer. The contact cut made in the gate oxide layer covering the substrate is made smaller than the poly deposited and patterned thereover. Damage to the substrate surface during the etching of the poly layer pattern is prevented by the presence of the gate oxide layer between the poly layer and the substrate. An ion implantation step performed early in the process forms a parasitic depletion mode channel under the region having an overlap of poly onto gate oxide. Consequently, though the gate oxide prevents the direct diffusion of dopant into the underlying substrate when conductors are formed by doping, the parasitic channel ohmically couples the poly interconnect layer to the diffused region in the substrate. The latter region is usually the S/D electrode of an IGFET. The composite process is compatible with the formation of self-aligned gates and conductively doped poly and substrate regions which are simultaneously doped with the same impurity.

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Fremont, CA, United States of America

Vinod K Dham