Texas Instruments Corporation

Vincent Maurice McNeil

Mark Stephen Rodder

Douglas Ticknor Grider

Jorge Adrian Kittl

E Ajith Amerasekera

Jorge A Kittl

A method to enhance the formation of nucleation sites on at least one narrow silicon structure comprises the step: forming at least one nucleation region ( ): masking the at least one narrow silicon structure ( ) with a mask ( ); treating the at least one nucleation region ( ) to enhance an ability of said region to form C54 nucleation sites; and removing the mask from the at least one narrow silicon structure ( ). In another embodiment, a silicon device capable of undergoing a phase transformation comprises at least one narrow silicon structure ( ) formed of TiSi ; and at least one nucleation region ( ) attached to the at least one narrow silicon region ( ), said at least one nucleation region ( ) having a width which is greater than a width of said at least one narrow silicon structure ( ) and said at least one nucleation region ( ) capable of generating a high density of C54 nucleation sites such that said high density of nucleation sites causes a phase transformation ( ) to propagate along the at least one silicon structure ( ).

Method to enhance the formation of nucleation sites on silicon structures and an improved silicon structure

A method for forming an integrated circuit having multiple gate oxide thicknesses is disclosed herein. The circuit (10) is processed up to gate oxide formation. A pattern (36) is then formed exposing areas of the circuit where a thinner gate oxide (20) is desired. These areas are then implanted with a halogen species such as fluorine or chlorine, to retard oxidation. The pattern (36) is then removed and an oxidation step is performed. Oxidation is selectively retarded in areas (14) previously doped with the halogen species but not in the remaining areas (12). Thus, a single oxidation step may be used to form gate oxides (20,22) of different thicknesses.

Selective area halogen doping to achieve dual gate oxide thickness on a

A technique for providing a design window for scaled technologies in which good electrostatic discharge/electrical over stress damage and optimum transistor operation can be achieved without the use of additional masks or design steps. The M, beta, and R.sub.sub parameters of the NMOS transistor 13 and associated parasitic npn transistor 10 are selected to provide the design window.

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Dallas, TX, United States of America

Vincent Maurice McNeil