Femtometrix, Inc.

Micron Technology Incorporated

Finscale Inc.

Other

Pdf Solutions, Incorporated

Viktor Koldiaev

John Paul Changala

Marc Kryger

Serguei Okhonin

Mikhail Nagoga

Yogesh Luthra

Jianing Shi

Rimma A Pirogova

Pierre C Fazan

Michael Allen Van Buskirk

Christian Caillat

Jungtae Kwon

Jeff Babock

George Cheroff

Marc Christopher Kryger

Various approaches can be used to interrogate a surface such as a surface of a layered semiconductor structure on a semiconductor wafer. Certain approaches employ Second Harmonic Generation and in some cases may utilize pump and probe radiation. Other approaches involve determining current flow from a sample illuminated with radiation. Decay constants can be measured to provide information regarding the sample. Additionally, electric and/or magnetic field biases can be applied to the sample to provide additional information.

Wafer metrology technologies

Semiconductor metrology systems based on directing radiation on a wafer, detecting second harmonic generated (SHG) radiation from the wafer and correlating the second harmonic generated (SHG) signal to one or more electrical properties of the wafer are disclosed. The disclosure also includes parsing the SHG signal to remove contribution to the SHG signal from one or more material properties of the sample such as thickness. Systems and methods described herein include machine learning methodologies to automatically classify obtained SHG signal

Systems for parsing material properties from within SHG signals

Various approaches to can be used to interrogate a surface such as a surface of a layered semiconductor structure on a semiconductor wafer. Certain approaches employ Second Harmonic Generation and in some cases may utilize pump and probe radiation. Other approaches involve determining current flow from a sample illuminated with radiation.

Pump and probe type second harmonic generation metrology

Field-biased second harmonic generation metrology

Semiconductor metrology systems based on directing radiation on a wafer, detecting second harmonic generated (SHG) radiation from the wafer and correlating the second harmonic generated (SHG) signal to one or more electrical properties of the wafer are disclosed. The disclosure also includes parsing the SHG signal to remove contribution to the SHG signal from one or more material properties of the sample such as thickness. Systems and methods described herein include machine learning methodologies to automatically classify obtained SHG signal.

Semiconductor metrology systems based on directing radiation on a wafer, detecting second harmonic generated (SHG) radiation from the wafer and correlating the second harmonic generated (SHG) signal to one or more electrical properties of the wafer are disclosed. The disclosure also includes parsing the SHG signal to remove contribution to the SHG signal from one or more material properties of the sample such as thickness. Systems and methods described herein include machine learning methodologies to automatically classify obtained SHG signal data from the wafer based on an electrical property of the wafer.

The present invention is a semiconductor device comprising a semiconducting low doped vertical super-thin body (VSTB) formed on Dielectric Body Wall (such as STI-wall as isolating substrate) having the body connection to bulk semiconductor wafer on the bottom side, isolation on the top side, and the channel, gate dielectric, and gate electrode on opposite to STI side surface. The body is made self-aligned to STI hard mask edge allowing tight control of body thickness. Source and Drain are made by etching holes vertically in STI at STI side of the body and filling with high doped crystalline or poly-Si appropriately doped with any appropriate silicides/metal contacts or with Schottky barrier Source/Drain. Gate first or Gate last approaches can be implemented. Many devices can be fabricated in single active area with body isolation between the devices by iso-plugs combined with gate electrode isolation by iso-trenches. The body can be made as an isolated nano-plate or set nano-wire MOSFET's on the STI wall to form VSTB SOI devices.

Vertical super-thin body semiconductor on dielectric wall devices and methods of their fabrication

Techniques for providing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as an apparatus including a first region and a second region. The apparatus may also include a body region disposed between the first region and the second region and capacitively coupled to a plurality of word lines, wherein each of the plurality of word lines is capacitively coupled to different portions of the body region.

Techniques for providing a semiconductor memory device

Techniques for providing a semiconductor memory device are disclosed. In one embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. Each memory cell may include a first region connected to a source line extending in a first orientation, a second region connected to a bit line extending a second orientation, and a body region spaced apart from and capacitively coupled to a word line, wherein the body region is electrically floating and disposed between the first region and the second region. The semiconductor device may also include a first barrier wall extending in the first orientation of the array and a second barrier wall extending in the second orientation of the array and intersecting with the first barrier wall to form a trench region configured to accommodate each of the plurality of memory cells.

Growing community of inventors

Morgan Hill, CA, United States of America

Viktor Koldiaev