Cirrus Logic Inc.

Vikram Shenoy

Dimitris Pantelakis

Robert Arthur Jensen

John L Melanson

Mail Khoi

Memory address decoder circuitry including a decoder for activating a corresponding memory access control conductor in response to registered address bits. An address register stores received address bits for presentation to the inputs of the decoder and includes reset circuitry for resetting the outputs of the address register to an inactive state during an inactive time period to reduce transition glitches in the decoder during latching in a subsequent active period.

Glitch-free memory address decoding circuits and methods and memory subsystems using the same

A stress test circuit and method for static random access memory (&ldquo;SRAM&rdquo;) cells of an SRAM device are disclosed. The stress test component has a resistance element and a switch component to electrically couple the resistance element between a bit line and complementary bit line of an SRAM cell storing a digital value. Stress test component is activated to electrically couple the resistance element to the bit line and complementary bit line. An electrical path is created causing a voltage on an SRAM circuit path maintaining the digital value to be pulled in one direction by a stress current. The electrical path causes another voltage on another SRAM circuit path maintaining a complementary digital value to be pulled in an opposite direction by the stress current. The SRAM cell is then read to determine whether the digital value has changed state.

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Austin, TX, United States of America

Vikram Shenoy