International Business Machines Corporation

Hitachi Global Storage Technologies Netherlands B.v.

Globalfoundries Inc.

Globalfoundries U.S. 2 LLC

Vijayeshwar Das Khanna

Sri Muthuthamby Sri-Jayantha

Arun Sharma

Gerard McVicker

Hien Phu Dang

Suresh Kumar

David John Russell

Anson Jay Call

David L Questad

Muthuthamby Sri-Jayantha

Krishna R Tunga

Lorenzo Valdevit

Edmund D Blackshear

Kiyoshi Satoh

Jennifer V Muncy

Zine-Eddine Boutaghou

Thomas R Albrecht

Gareth Geoffrey Hougham

Xiao Hu Liu

Ferdinand Hendriks

Douglas Oliver Powell

Akihiko Aoyagi

Tatsuo Nakamoto

Jennifer V Muney

Mitsuro Ohta

Joseph Paul Kuczynski

Daniel C Edelstein

Gordon James Smith

David Clifford Long

Hiroshi Matsuda

Qinghuang Lin

Paul Stephen Andry

Roy Rongqing Yu

Marc Adam Bergendahl

Arvind Kumar Sinha

Kamal Kumar Sikka

Robert L Wisnieff

Steven Alan Cordes

Vinod Kamath

Fu-Ying Huang

Hiroyuki Mori

Naoyuki Kagami

Mutsuro Ohta

Yang Liu

Virendra R Jadhav

Ravi K Bonam

Keishi Takahashi

Kohji Takahashi

Peter Jerome Sorce

Alok Kumar Lohia

Yuzo Nakagawa

Dale Curtis McHerron

Jung H Yoon

Isabel De Sousa

Mohammed S Shaikh

Eric Gung-Hwa Lean

Ichiroh Koyanagi

Kohji Serizawa

Oswald J Mantilla

Maryse Cournoyer

Pascale Gagnon

Catherine Dufort

Kenneth F Latzko

Charles C Bureau

Robert M Crone

Jagdeep Tahliani

Koji Kawabata

Dishit Paresh Parekh

Evan G Colgan

Gerard MoVicker

Shuo H Chang

A direct bonded heterogeneous integration (DBHi) device includes a substrate including a trench formed in a top surface of the substrate. The DBHi device further includes a first chip coupled to the substrate on a first side of the trench by a plurality of first interconnects. The DBHi device further includes a second chip coupled to the substrate on a second side of the trench by a plurality of second interconnects. The second side of the trench is arranged opposite the first side of the trench. The DBHi device further includes a bridge coupled to the first chip and to the second chip by a plurality of third interconnects such that the bridge is suspended in the trench. The DBHi device further includes a non-conductive paste material surrounding the plurality of third interconnects to further couple the bridge to the first chip and to the second chip.

Direct bonded heterogeneous integration silicon bridge

A server node connection system uses two or more proximity sensors per server node to determine progressive, real time changes in wipe length for each individual connector on the node that is connected to an opposing header connector on header connected to a midplane of the server assembly/rack. The system is capable of scanning, monitoring, trending, and alarming.

Server node connector mating condition health monitoring and reporting

An organic substrate and method of making with optimal thermal warp characteristics is disclosed. The organic substrate has one or more top layers and one or more bottom layers. A chip footprint region is a surface region on each of the top and bottom layers that is defined as the projection of one or more semiconductor chips (chips) on the surface of each of the top and bottom layers. One or more top removal patterns are located on and may or may not remove material from the surface of one or more of the top layers within the chip footprint region of the respective top layer. One or more bottom removal patterns are located on and remove material from the surface of one or more of the bottom layers outside the chip footprint region of the respective bottom layer. The removal of the material from one or more of the top layers and/or bottom layers changes and optimizes a thermal warp of the organic substrate. In some embodiments, a Shape Inversion Temperature (SIT) of the substrate is made equal to or above a reflow temperature.

Optimum warp in organic substrates

Server node connnector mating condition health monitoring and reporting

An electrical contact upon an interposer and/or upon a processing device includes a minor axis and a major axis. The contact is positioned such that the major axis is generally aligned with the direction of expansion of the interposer and/or the processing device. The electrical contact may further be positioned within a power/ground or input/output (I/O) region of the interposer and/or processing device. The electrical contact may further be positioned within a center region that is surrounded by a perimeter region of the interposer and/or the processing device. The dimensions or aspect ratios of major and minor axes of neighboring electrical contacts within an electrical contact grid may differ relative thereto. Further, the angle of respective major and minor axes of neighboring electrical contacts within the electrical contact grid may differ relative thereto.

Method of fabricating contacts of an electronic package structure to reduce solder interconnect stress

A first electrical contact and second contact is upon an interposer and/or upon a processing device. The first contact includes a minor axis and a major axis. The second contact includes diameter axes. The first contact is positioned such that the major axis is generally aligned with the direction of expansion of the interposer and/or the processing device. The first electrical contact may further be positioned within a power/ground or input/output (I/O) region of the interposer and/or processing device. The first electrical contact may further be positioned within a center region that is surrounded by a perimeter region of the interposer and/or the processing device. The dimensions or aspect ratios of major and minor axes of neighboring first electrical contacts within an electrical contact grid may differ relative thereto. Further, the angle of respective major and minor axes of neighboring first electrical contacts within the electrical contact grid may differ relative thereto.

Reduction of solder interconnect stress

Method of designing a laminate substrate having upper laminate layers and an equal plurality of lower laminate layers including: dividing the laminate substrate into regions having corresponding laminate layer pairs consisting of an upper laminate layer and a lower laminate layer; calculating a net stretching value for each corresponding laminate layer pair in each region to result in net stretching values in each region; summing the net stretching values in each region to result in a net stretching value for each region proportional to a curvature of each local region; calculating a relative out-of-plane displacement for the laminate substrate from the curvature of each local region; calculating a predicted thermal warpage for the laminate substrate; and finalizing a design of the laminate substrate when the predicted thermal warpage is within a predetermined acceptable range.

Laminate substrate thermal warpage prediction for designing a laminate substrate

An approach is provided in which a laminate substrate includes top layers, bottom layers, and a core layer. The top layers are positioned between the core layer and a top surface metallurgy (TSM) layer and include at least one top conductive layer. The bottom layers are positioned between the core layer and a bottom surface metallurgy (BSM) layer and include at least one bottom conductive layer includes a material void pattern that is based upon the top conductive layer and reduces warpage of the laminate substrate.

Copper feature design for warpage control of substrates

A mechanism to attach a die to a substrate and method of use are disclosed. The vacuum carrier includes a frame composed of material compatible with solder reflow process. The vacuum carrier further includes a vacuum port extending from a top surface to an underside surface of the frame. The vacuum carrier further includes a seal mechanism provided about a perimeter on the underside surface of the frame of the vacuum carrier. The frame and seal mechanism are structured to maintain a flatness of a die attached to the vacuum carrier by a vacuum source during the solder reflow process.

Mechanism to attach a die to a substrate

A method of predicting warpage of a laminate is disclosed in which in-plane copper imbalance is calculated. A method of designing an organic build-up laminate is provided in which in-plane copper imbalance is calculated and imbalances are corrected.

In-plane copper imbalance for warpage prediction

A structure and method of mounting a heat sink having a body and mounting points configured so as to connect to a mounting medium, at least one of the mounting points being configured to allow movement in a thermally-induced expansion direction.

Method and system for thermomechanically decoupling heatsink

An electronic module includes a substrate including at least one structure that reduces stress flow through the substrate, wherein the structure includes at least one trench in a surface of the substrate, and a plurality of capacitor legs disposed on an upper surface of the substrate.

Electronic components on trenched substrates and method of forming same

A clamping apparatus applies a force to a workpiece during processing. The clamping apparatus includes a base defining a work area configured to receive a joined structure having multiple elements. The base defines a recess in the work area. An adjustable mechanism is configured to releasably couple to the base and apply a adjustable downward force to the joined structure to bend the joined structure downwardly into the recess during a process. A resilient plunger is part of the adjustable mechanism. The resilient plunger extends downwardly from a top plate of the adjustable mechanism, and the resilient plunger is configured to contact a top of a first element of the joined structure to apply the downward force.

Constrained die adhesion cure process

A vacuum carrier can be employed to provide a partial vacuum on a back side surface of a substrate thereby holding the substrate flat against a rigid surface of the carrier throughout the duration of a bonding process. The magnitude of vacuum can be optimized to limit the warping of the substrate during and after bonding with another substrate, and to limit the mechanical stress induced in the solder balls during cooling. The vacuum carrier can include a base plate, a seal plate with at least one opening configured to accommodate at least one substrate, and vacuum seal elements configured to create a vacuum environment that pushes the substrate against the base plate when the vacuum carrier is under vacuum. The configuration of the vacuum carrier is chosen to avoid distortion of the substrate due to the vacuum seal elements, while allowing adjustment of the magnitude of the partial vacuum.

Vacuum carriers for substrate bonding

Growing community of inventors

Ossining, NY, United States of America

Vijayeshwar Das Khanna