Intel Corporation

Vijayakumar S Ramachandrarao

David H Gracias

Hyun-Mog Park

Robert B Turkot, Jr

Justin K Brask

Grant M Kloster

Shriram Ramanathan

Subramanyam Iyer

Adrien Lavoie

Kevin O'Brien

Manish Chandhok

Boyan Boyanov

Robert L Bristol

Robert P Meagley

Arnel M Fajardo

Heidi B Cao

Shan Christopher Clark

Bob Turkot

Supercritical carbon dioxide may be utilized to remove resistant residues such as those residues left when etching dielectrics in fluorine-based plasma gases. The supercritical carbon dioxide may include an oxidizer in one embodiment.

Cleaning residues from semiconductor structures

The microelectronic device interconnects are fabricated by a process that utilizes a silicon-based interlayer dielectric material layer, such as carbon-doped oxide, and a chemical mixture selective to materials used in the formation of the interconnects, including, but not limited to, copper, cobalt, tantalum, and/or tantalum nitride, to remove the interlayer dielectric material layer between adjacent interconnects thereby forming air gaps therebetween.

Methods for the formation of interconnects separated by air gaps

Embodiments of the invention include apparatuses and methods relating to air gap interconnect structures having interconnects protected by a sealant. In various embodiments, the sealant includes alumina or silicon nitride. In some embodiments, the interconnect structures include cobalt alloy liners and cobalt shunts to encase a conductive material.

Sealants for metal interconnect protection in microelectronic devices having air gap interconnect structures

A porous dielectric layer is formed on a substrate. Aluminum is incorporated in the porous dielectric layer with a pattern process using an Aluminum gas precursor. The incorporated Aluminum improves the mechanical properties of the porous dielectric layer.

Aluminum incorporation in porous dielectric for improved mechanical properties of patterned dielectric

Electric fields may be advantageously used in various steps of photolithographic processes. For example, prior to the pre-exposure bake, photoresists that have been spun-on the wafer may be exposed to an electric field to orient aggregates or other components within the unexposed photoresist. By aligning these aggregates or other components with the electric field, line edge roughness may be reduced, for example in connection with 193 nanometer photoresist. Likewise, during exposure, electric fields may be applied through uniquely situated electrodes or using a radio frequency coil. In addition, electric fields may be applied at virtually any point in the photolithography process by depositing a conductive electrode, which is subsequently removed during development. Finally, electric fields may be applied during the developing process to improve line edge roughness.

Enhancing photoresist performance using electric fields

A method for sealing a porous dielectric layer atop a substrate, wherein the dielectric layer is patterned to form at least a trench and at least a via, comprises applying a first plasma to a surface of the dielectric layer to silanolize the surface, treating the surface of the dielectric layer with a silazane to form a monolayer of silane molecules on the surface, and applying a second plasma to the surface of the dielectric layer to induce a polymerization of at least a portion of the silane molecules. The polymerized silane molecules form a cross-linked matrix that builds over a substantial portion of the surface of the dielectric layer and seals at least some of the exposed pores.

Sealing porous dielectric material using plasma-induced surface polymerization

Systems and techniques relating to etching vias in integrated circuit devices, in one implementation, include: providing a dielectric material and a conductive material, removing a first portion of the dielectric material to form a hole in the dielectric material, performing a tapering etch that removes a second portion of the dielectric material to form a via that touches down on the conductive material, and laterally expanding a bottom dimension of the via without a significant increase in a depth of the via. The technique can also include: providing a substrate with the dielectric material and the conductive material attached without an associated etch stop layer, removing the first portion at a high etch rate, controlling ion bombardment and plasma chemistry to form a sloped bottom of the via, and performing an intensive ion bombarding plasma etch, laterally expanding the via bottom.

Via etch process

A method for wafer stacking employing substantially uniform copper structures is described herein.

Method for wafer stacking using copper structures of substantially uniform height

A thin hard mask is formed over a semiconductor substrate. The thin hard mask allows diffusion of a sacrificial material or pore-forming agent therethrough to form an underlying air gap or porous dielectric region. The thin hard mask may be a polymer or an initially porous material that may be later densified. The thin hard mask may be used to prevent etch steps used in forming an unlanded via from reaching layers below the hard mask.

Forming thin hard mask over air gap or porous dielectric

Suitable particles may be deposited within an extremely small high-aspect ratio via by flowing the particles in a suspension using supercritical carbon dioxide. The particles may be made up of diblock copolymers or silesquioxane-based materials or oligomers of phobic homopolymers or pre-formed silica-based particles stabilized using diblock copolymers and may include chemical initiators to permit in situ polymerization within the via.

Filling small dimension vias using supercritical carbon dioxide

Processing problems associated with porous low-k dielectric materials are often severe. Exposure of low-k materials to plasma during feature etching, ashing, and priming steps has deleterious consequences. For porous, silicon-based low-k dielectric materials, the plasma depletes a surface organic group, raising the dielectric constant of the material. In the worst case, the damaged dielectric is destroyed during the wet etch removal of the antireflective coating in the via-first copper dual-damascene integration scheme. This issue is addressed by exposing the dielectric to silane coupling agents at various stages of etching and cleaning. Chemical reactions with the silane coupling agent both replenish the dielectric surface organic group and passivate the dielectric surface relative to the surface of the antireflective coating.

Replenishment of surface carbon and surface passivation of low-k porous silicon-based dielectric materials

Supercritical carbon dioxide may be utilized to clean metal lines (e.g. copper, cobalt). The supercritical carbon dioxide cleans may include hydrogen gas in one embodiment, hydrofluoric acid in another embodiment, and hexafluoroacetyl acetone as a metal-binding ligand in another embodiment.

Supercritical carbon dioxide-based cleaning of metal lines

Polymer aggregates in a photoresist layer may be dissolved or reduced in dimension by treatment with supercritical carbon dioxide. The supercritical carbon dioxide may be used before and/or after development of the photoresist. The SCCOtreatment causes swelling of the photoresist and may allow polymer aggregates in the photoresist to be dissolved. Controlled release of the carbon dioxide de-swells the photoresist, resulting in reduced line edge roughness of openings in the photoresist and reduced resistance of metal lines formed in the openings.

Supercritical carbon dioxide to reduce line edge roughness

Wafer stacking employing substantially uniform copper structures is described herein.

Wafer stacking using interconnect structures of substantially uniform height

Supercritical carbon dioxide may be utilized to remove resistant residues such as those residues left when etching dielectrics in fluorine-based plasma gases. The supercritical carbon dioxide may include an ionic liquid in one embodiment.

Growing community of inventors

Hillsboro, OR, United States of America

Vijayakumar S Ramachandrarao