Taiwan Semiconductor Manufacturing Comp. Ltd.

Victor C Y Chang

Harry Chuang

Hsin-Yi Lee

Chien-Wen Chen

Yung-Shun Chen

Yu-Tai Chia

Shang Y Hou

Chung-Shi Chiang

Each of a method for determining a parasitic capacitance and an apparatus for determining the parasitic capacitance provides for an experimental correlation within a parasitic capacitance model of a series of conductor layer nominal dimensions and spacings with a process related deviation to provide a series of conductor layer actual dimensions and spacings. The method and the apparatus further provide for determining the parasitic capacitance while employing the conductor layer actual dimensions and spacings. The parasitic capacitance is thus determined with enhanced accuracy.

Process related deviation corrected parasitic capacitance modeling method

A new method to determine a parameter of a damascene interconnect in an integrated circuit device is achieved. Drawn dimensions and local pattern density of a damascene interconnect are extracted in an integrated circuit device. A parameter of the damascene interconnect is calculating using the drawn dimensions and the local pattern density to select a per unit value from a set of per unit values measured over a range of drawn dimension and pattern density combinations. The method may be used to improve the accuracy of extracted damascene metal line resistance and parasitic capacitance.

Methodology to characterize metal sheet resistance of copper damascene process

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Tucheng, Taiwan

Victor C Y Chang