Freescale Semiconductor,inc.

Veronique C Macary

Jiang-kai Zuo

Won Gi Min

Hongning Yang

An embodiment of an N-channel device has a lightly doped substrate in which adjacent or spaced-apart P and N wells are provided. A lateral isolation wall surrounds at least a portion of the substrate and is spaced apart from the wells. A first gate overlies the P well or the substrate between the wells or partly both. A second gate, spaced apart from the first gate, overlies the N-well. A body contact to the substrate is spaced apart from the isolation wall by a first distance within the space charge region of the substrate to isolation wall PN junction. When the body contact is connected to the second gate, a predetermined static bias Vgis provided to the second gate, depending upon the isolation wall bias (Vbias) and the first distance.

Dual gate LDMOS devices

Embodiments of microelectronic assemblies are provided. First and second semiconductor devices are formed over a substrate having a first dopant type at a first concentration. First and second buried regions having a second dopant type are formed respectively below the first and second semiconductor devices with a gap therebetween. At least one well region is formed over the substrate and between the first and second semiconductor devices. A barrier region having the first dopant type at a second concentration is formed between and adjacent to the first and second buried regions such that at least a portion of the barrier region extends a depth from the first and second semiconductor devices that is greater or equal to the depth of the buried regions.

Microelectronic assemblies with improved isolation voltage performance

An N-channel device () is described having a very lightly doped substrate () in which spaced-apart P () and N () wells are provided, whose lateral edges () extending to the surface (). The gate () overlies the surface () between the P () and N () wells. The P-well edge () adjacent the source () is substantially aligned with the left gate edge (). The N-well edge () lies at or within the right gate edge (), which is spaced a first distance () from the drain (). The N-well () desirably includes a heavier doped region () in ohmic contact with the drain () and with its left edge () located about half way between the right gate edge () and the drain (). A HALO implant pocket () is provided underlying the left gate edge () using the gate () as a mask. The resulting device () operates at higher voltage with lower Rdson, less HCI and very low off-state leakage. P and N dopants are interchanged to provide P-channel devices.

LDMOS device and method

A method for forming a microelectronic assembly and a microelectronic assembly are provided. First and second semiconductor devices () are formed over a substrate () having a first dopant type at a first concentration. First and second buried regions () having a second dopant type are formed respectively below the first and second semiconductor devices with a gap () therebetween. At least one well region () is formed over the substrate and between the first and second semiconductor devices. A barrier region () having the first dopant type at a second concentration is formed between and adjacent to the first and second buried regions such that at least a portion of the barrier region extends a depth () from the first and second semiconductor devices that is greater or equal to the depth of the buried regions.

Microelectronic assembly with improved isolation voltage performance and a method for forming the same

An N-channel device () is described having a lightly doped substrate (') in which adjacent or spaced-apart P (&#x2032;) and N () wells are provided. A lateral isolation wall () surrounds at least a portion of the substrate (&#x2032;) and is spaced apart from the wells (). A first gate (G) () overlies the P () well or the substrate (&#x2032;) between the wells () or partly both. A second gate (G) (), spaced apart from G(), overlies the N-well (). A body contact () to the substrate (&#x2032;) is spaced apart from the isolation wall () by a first distance () within the space charge region of the substrate (&#x2032;) to isolation wall () PN junction. When the body contact () is connected to G(), a predetermined static bias Vgis provided to G() depending upon the isolation wall bias (Vbias) and the first distance (). The resulting device () operates at higher voltage with lower Rdson and less HCI.

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Chandler, AZ, United States of America

Veronique C Macary