Taiwan Semiconductor Manufacturing Comp. Ltd.

United Microelectronics Corp.

Vencent Chang

Kuei Shun Chen

George Liu

Chin-Hsiang Lin

Norman Chen

Tsiao-Chen Wu

Hsiao-Tzu Lu

Hun-Jan Tao

Cheng-Lung Hung

Shang-Wen Chang

Peng-Fu Hsu

Yong-Tian Hou

Jhun Hua Chen

Jin Ying

Fong-Yu Yen

Lai Chien Wen

Lawrence Lin

Benjamin Szu-Min Lin

Chia-Chu Liu

I-Hsiung Huang

Yao-Ching Ku

Chih-Yang Yeh

Kuei-Chun Hung

Anseime Chen

Hui-Ling Huang

Cheng-Chung Chen

Keui Shun Chen

Andersen Chang

Ya-Hui Chang

System and method for enhancing optical lithography methodology for hole patterning in semiconductor fabrication are described. In one embodiment, a photolithography system comprises an illumination system for conditioning light from a light source, the illumination system producing a three-pore illumination pattern; a reticle comprising at least a portion of a pattern to be imaged onto a substrate, wherein the three-pore illumination pattern produced by the illumination system is projected through the reticle; and a projection lens disposed between the reticle and the substrate.

Methodology for implementing enhanced optical lithography for hole patterning in semiconductor fabrication

Contrast enhancing exposure apparatus and method for use in semiconductor fabrication are described. In one embodiment, a method for forming a pattern on a substrate, wherein the substrate includes a photoresist layer comprising photoacid generators ('PAGs') and photobase generators ('PBGs'), is described. The method includes dividing the pattern into two component patterns; exposing the photoresist layer of the substrate to UV light through a first mask corresponding to a first one of the component patterns; subsequent to the exposing the photoresist layer of the substrate to UV light through the first mask, exposing the photoresist layer of the substrate to UV light through a second mask corresponding to a second one of the component patterns, wherein the PAGs and PBGs disposed in areas of the photoresist layer that have been exposed to UV light at least twice are activated and wherein the activated PAGs neutralize the activated PBGs in areas of the photoresist layer that have been exposed to UV light at least twice.

Contrast enhancing exposure system and method for use in semiconductor fabrication

The method of patterning a photosensitive layer includes providing a substrate including a first layer formed thereon, treating the substrate including the first layer with cations, forming a first photosensitive layer over the first layer, patterning the first photosensitive layer to form a first pattern, treating the first pattern with cations, forming a second photosensitive layer over the treated first pattern, patterning the second photosensitive layer to form a second pattern, and processing the first layer using the first and second patterns as a mask.

Method for patterning a photosensitive layer

A method for etching an ultra thin film is provided which includes providing a substrate having the ultra thin film formed thereon, patterning a photosensitive layer formed over the ultra thin film, etching the ultra thin film using the patterned photosensitive layer, and removing the patterned photosensitive layer. The etching process includes utilizing an etch material with a diffusion resistant carrier such that the etch material is prevented from diffusing to a region underneath the photosensitive layer and removing portions of the ultra thin film underneath the photosensitive layer.

Method for etching an ultra thin film

A semiconductor device is disclosed that includes: a substrate; a first dielectric layer formed over the substrate and formed of a first high-k material, the first high-k material selected from the group consisting of HfO, HfSiO, HfSiON, HfTaO, HfTiO, HfTiTaO, HfAlON, and HfZrO; a second dielectric layer formed over the first dielectric layer and formed of a second high-k material, the second high-k material being different than the first high-k material and selected from the group consisting of HfO, HfSiO, HfSiON, HfTaO, HfTiO, HfTiTaO, HfAlON, and HfZrO; and a metal gate formed over the second dielectric layer. The first dielectric layer includes ions selected from the group consisting of N, O, and Si.

Semiconductor devices and methods with bilayer dielectrics

Provided is a semiconductor device. The device includes a substrate having a photo acid generator (PAG) layer on the substrate. The PAG layer is exposed to radiation. A photoresist layer is formed on the exposed PAG layer. The exposed PAG layer generates an acid. The acid decomposes a portion of the formed photoresist layer. In one embodiment, the PAG layer includes organic BARC. The decomposed portion of the photoresist layer may be used as a masking element.

Pattern formation in semiconductor fabrication

An integrated circuit device and method of making the integrated circuit device are disclosed. An exemplary apparatus includes: a semiconductor layer; and a dielectric layer on the semiconductor layer, the dielectric layer having conductive vias and dummy vias formed therein, wherein the conductive vias and dummy vias extend varying distances into the dielectric layer, the conductive vias extending through the dielectric layer to the semiconductor layer, and the dummy vias extending through the dielectric layer to a distance above the semiconductor layer.

Dummy vias for damascene process

A method of making an integrated circuit includes providing a low-k dielectric layer on a substrate, the low-k dielectric layer including or adjacent to a plurality of conductive features; patterning the low-k dielectric layer to form trenches; patterning the low-k dielectric layer to form conductive vias and dummy vias, wherein each of the conductive vias is aligned with at least one of the plurality of the conductive features and at least one of the trenches, and each of the dummy vias is a distance above the plurality of conductive features; filling the trenches, conductive vias, and dummy vias using one or more conductive materials; and planarizing the conductive material(s).

Provided is a method of fabricating a semiconductor device. The method includes providing a substrate, forming a photo acid generator (PAG) layer on the substrate, exposing the PAG layer to radiation, and forming a photoresist layer on the exposed PAG layer. The exposed PAG layer generates an acid. The acid decomposes a portion of the formed photoresist layer. In one embodiment, the PAG layer includes organic BARC. The decomposed portion of the photoresist layer may be used as a masking element.

Method of pattern formation in semiconductor fabrication

A semiconductor device is fabricated to include one or more sets of calibration patterns used to measure line pitch and line focus.

Semiconductor device having in-chip critical dimension and focus patterns

A semiconductor device is disclosed that includes: a substrate; a first high-k dielectric layer; a second high-k dielectric layer formed of a different high-k material; and a metal gate. In another form, a method of forming a semiconductor device is disclosed that includes: providing a substrate; forming a first high-k dielectric layer above the substrate; forming a second dielectric layer of a different high-k material above the first dielectric layer; and forming a gate structure above the second dielectric layer. In yet another form, a method of forming a semiconductor device is disclosed that includes: providing a substrate; forming an interfacial layer above the substrate; forming a first high-k dielectric layer above the interfacial layer; performing a nitridation technique; performing an anneal; forming a second high-k dielectric layer of a different high-k material above the first dielectric layer; and forming a metal gate structure above the second dielectric layer.

An immersion lithography process is described as follows. A photoresist layer and a protective layer are sequentially formed on a material layer, and then an immersion exposure step is performed to define an exposed portion and an unexposed portion in the photoresist layer. A solubilization step is conducted to solubilize the protective layer on the exposed portion of the photoresist layer, and then a development step is conducted to remove the exposed portion of the photoresist layer and the protective layer thereon. Since the photoresist layer is covered with the protective layer, the chemicals in the photoresist layer do not diffuse into the immersion liquid to cause contamination. The protective layer can be patterned simultaneously in the development step, and no extra step is required to remove the protective layer. Therefore, the whole lithography process is not complicated.

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Hsinchu, Taiwan

Vencent Chang