International Business Machines Corporation

Globalfoundries Inc.

Adeia Semiconductor Bonding Technologies Inc.

Renesas Electronics Corporation

Globalfoundries U.S. Inc.

Kabushiki Kaisha Toshiba

Freescale Semiconductor,inc.

Stmicroelectronics Gmbh

Globalfoundries U.S. 2 LLC

Elpis Technologies Inc.

Adeia Semiconductor Solutions LLC

Veeraraghavan S Basker

Kangguo Cheng

Junli Wang

Tenko Yamashita

Theodorus E Standaert

Chun-chen Yeh

Ali Khakifirooz

Alexander Reznicek

Zuoguang Liu

Ruilong Xie

Shogo Mochizuki

Andrew Mark Greene

Effendi Leobandung

Oleg Gluschenkov

Julien Frougier

Huiming Bu

Charles W Koburger, Iii

Juntao Li

Sivananda K Kanakasabapathy

Bruce Bennett Doris

Nicolas J Loubet

Johnathan E Faltermeier

Reinaldo Ariel Vega

Dechao Guo

Pouya Hashemi

Toshiharu Furukawa

Hemanth Jagannathan

Hariklia Deligianni

Praneet Adusumilli

Chung-Hsun Lin

Chun-Chen Yeh

William R Tonti

Andres Bryant

Vamsi Krishna Paruchuri

David V Horak

Hui Zang

Jingyun Zhang

Robert Russell Robison

Wilfried Haensch

Pranita Kerber

Rajarao Jammy

Huimei Zhou

Carl John Radens

Chanro Park

Terence B Hook

Christopher J Penny

Su Chen Fan

Henry K Utomo

Takashi Ando

Steven J Holmes

Xin Miao

Keith E Fogel

Shom Ponoth

Guillaume Bouche

Balasubramanian S Haran

Emre Alptekin

Dieter F Wendel

Byeong Yeol Kim

Xinhui Wang

Chih-Chao Yang

Lawrence Alfred Clevenger

Mark Charles Hakey

Balasubramanian Pranatharthiharan

Lars W Liebmann

Cyril Cabral, Jr

Qing Liu

Katherine Lynn Saenger

Dominic Joseph Schepis

Sanjay C Mehta

Martin Michael Frank

Thomas N Adam

Ravikumar Ramachandran

John Michael Cotte

Laertis Economikos

Kisik Choi

Eduard Albert Cartier

Brian Joseph Greene

Richard Quimby Williams

Emanuel Israel Cooper

Haigou Huang

Ramachandra Divakaruni

Keith Kwong Hon Wong

Ruqiang Bao

Zhenxing Bi

Soon-Cheon Seo

Heng Wu

Kern Rim

Jeffrey Bowman Johnson

Babar Ali Khan

Lubomyr Taras Romankiw

Pranita Kulkarni

Xuefeng Liu

Joshua M Rubin

Albert Manhee Chu

Eric R Miller

Anthony I Chou

Indira P Seshadri

Vimal Kumar Kamineni

Viraj Yashawant Sardesai

Lan Yu

A via connection layer for an electronic package and method for fabricating a via connection layer are provided. The via connection layer includes asymmetric via(s) formed in the via connection layer. The asymmetric via include a first sidewall with a first slope angle in a first direction and a second sidewall, where the second sidewall includes a second slope angle in the first direction.

Enhanced linerless vias

A gate-all-around field effect transistor device is provided. The gate-all-around field effect transistor device includes one or more channel layers on a substrate. The gate-all-around field effect transistor device further includes an inner spacer wrapped around four sides of an end portion of each of the one or more channel layers. The gate-all-around field effect transistor device further includes a portion of an inner spacer liner between a portion of an upper most channel layer and a portion of an outer spacer.

Gate-all-around field-effect-transistor with wrap-around-channel inner spacer

A CMOS (complementary metal-oxide semiconductor) device includes an n-channel metal-oxide semiconductor (NMOS) device, a p-channel metal-oxide semiconductor (PMOS) device, the NMOS and the PMOS device surrounded by a first dielectric material, the NMOS device separated from the PMOS device by a second dielectric material, a first NMOS gate separated from a first PMOS gate by the second dielectric material, a second NMOS gate electrically connected to a second PMOS gate by a metal link disposed between the NMOS gate and the PMOS gate, the metal link disposed above the second dielectric material, a first source/drain (S/D) contact disposed above the second dielectric material, the first S/D contact disposed in contact with both NMOS S/D region and a PMOS S/D region, and a second S/D contact disposed adjacent to the second dielectric material, the second S/D contact disposed in contact with a single S/D region.

Semiconductor device having hybrid middle of line contacts

Embodiments herein describe semiconductor devices with single diffusion breaks that are narrower than the gates of transistors in those devices. That is, rather than forming the diffusion breaks using a dummy gate (which would result in the diffusion breaks having the same width as the gates of the transistors) the embodiments herein use different means to establish the width of the diffusion break. As a result, the diffusion break can be narrower than traditional diffusion breaks formed using dummy gates, thereby saving area in the semiconductor device.

Narrowing single diffusion break

A nanosheet semiconductor device includes channel nanosheets each connected to a source/drain region that has a front surface, a rear surface, and an internal recess between the front surface and the rear surface. The device further includes a source/drain region contact in physical contact with the V shaped internal recess, with the front surface, and with the rear surface. The device may be fabricated by forming the source/drain region, recessing the source/drain region, and by forming a sacrificial source/drain region upon and around the recessed source/drain region. The sacrificial source/drain region may be removed and the source/drain region contact may be formed in place thereof.

Wraparound contact with reduced distance to channel

A semiconductor device includes one or more fins extending from a substrate, the one or more fins having source/drain epitaxial grown material (S/D epitaxy) thereon that merges one or more fins, a gate formed over the one or more fins, the gate including high k metal gate disposed between gate spacers and a metal liner over the S/D epitaxy and sides of the gate spacers. The gate includes a self-aligned contact cap over the HKMG and the metal liner.

Formation of trench silicide source or drain contacts without gate damage

Embodiments of the present invention are directed to processing methods and resulting structures for co-integrating gate-all-around (GAA) nanosheets and comb-nanosheets on the same chip, wafer, or substrate. In a non-limiting embodiment of the invention, a GAA nanosheet device is formed in a first region of a substrate. The GAA nanosheet device includes a first nanosheet stack, a second nanosheet stack, and a first fin spacing distance between the first nanosheet stack and the second nanosheet stack. A comb-nanosheet device is formed in a second region of a substrate. The comb-nanosheet device includes a third nanosheet stack, a fourth nanosheet stack, and a second fin spacing distance between the third nanosheet stack and the fourth nanosheet stack that is less than the first fin spacing distance.

Co-integrating gate-all-around nanosheet transistors and comb-nanosheet transistors

FinFET devices and processes to prevent fin or gate collapse (e.g., flopover) in finFET devices are provided. The method includes forming a first set of trenches in a semiconductor material and filling the first set of trenches with insulator material. The method further includes forming a second set of trenches in the semiconductor material, alternating with the first set of trenches that are filled. The second set of trenches form semiconductor structures which have a dimension of fin structures. The method further includes filling the second set of trenches with insulator material. The method further includes recessing the insulator material within the first set of trenches and the second set of trenches to form the fin structures.

FinFET devices

A method of fabricating a static random-access memory (SRAM) device includes forming a sacrificial material and replacing the sacrificial material with a metal to form a cross-couple contact on a metal gate stack. A portion of the metal gate stack directly contacts each of a sidewall and an endwall of the cross-couple contact.

Replacement gate cross-couple for static random-access memory scaling

A semiconductor structure may include one or more nanosheet field-effect transistors formed on a first portion of a substrate, and one or more fin field-effect transistors formed on a second portion of the substrate. A source drain of the one or more nanosheet field-effect transistors or a gate of the one or more nanosheet field-effect transistors may be separated from the substrate by an isolation layer. A source drain of the one or more fin field-effect transistors or a gate of the one or more fin field-effect transistors may be in direct contact with the substrate. The semiconductor structure may include a gate spacer surrounding the gate of the one or more nanosheet field-effect transistors and the gate of the one or more fin field-effect transistors.

Gate-all-around nanosheet field effect transistor integrated with fin field effect transistor

Embodiments are disclosed for a system. The system includes a semiconductor structure. The semiconductor structure includes a dielectric liner that wraps around a top and one side of a substrate island. The dielectric liner separates a substrate from a gate stack. Further, the system includes an access trench in physical contact with the dielectric liner.

Late replacement bottom isolation for nanosheet devices

A semiconductor structure includes a first set of fins and a second set of fins, a dielectric pillar disposed between the first set of fins and the second set of fins, a bottom source/drain (S/D) region directly contacting a bottom surface of the first and second set of fins, and a top S/D region directly contacting a top surface of the first and second set of fins. A high-k metal gate (HKMG) is disposed between fins of the first set of fins and between fins of the second set of fins. The HKMG directly contacts sidewalls of the dielectric pillar. A width of the HKMG between the first set of fins is equal to a width of the HKMG between the second set of fins.

Vertical FET replacement gate formation with variable fin pitch

A semiconductor device fabricated by forming FET fins from a layered semiconductor structure. The layered semiconductor structure incudes a sacrificial layer. Further by forming dummy gate structures on the FET fins, recessing the FET fins between dummy gate structures, growing source-drain regions between FET fins and the sacrificial layer, replacing active region dummy gate structures with high-k metal gates structures, and replacing the sacrificial layer with a dielectric isolation material, wherein the dielectric isolation material extends across the active region.

Field effect transistors with bottom dielectric isolation

In one embodiment a semiconductor structure comprises a semiconductor substrate, a trench dielectric layer disposed in a trench of the semiconductor substrate, a first source/drain region disposed in contact with the semiconductor substrate, a gate and a second source/drain region. The gate is disposed between the first source/drain region and the second source/drain region. The semiconductor structure further comprises a dielectric isolation layer disposed between the semiconductor substrate and the second source/drain region.

Electrostatic discharge diode having dielectric isolation layer

A method of forming a semiconductor device that includes forming a fin structure from a bulk semiconductor substrate and forming an isolation region contacting a lower portion of a sidewall of the fin structure, wherein an upper portion of the sidewall of the fin structure is exposed. A sacrificial spacer is formed on the upper portion of the sidewall of the fin structure. The isolation regions are recessed to provide an exposed section of the sidewall of the fin structure. A doped semiconductor material is formed on the exposed section of the lower portion of the sidewall of the fin structure. Dopant is diffused from the doped semiconductor material to a base portion of the fin structure.

Punch through stopper in bulk finFET device

Growing community of inventors

Schenectady, NY, United States of America

Veeraraghavan S Basker