International Business Machines Corporation

Globalfoundries Inc.

Adeia Semiconductor Bonding Technologies Inc.

Renesas Electronics Corporation

Globalfoundries U.S. Inc.

Kabushiki Kaisha Toshiba

Freescale Semiconductor,inc.

Stmicroelectronics Gmbh

Globalfoundries U.S. 2 LLC

Elpis Technologies Inc.

Adeia Semiconductor Solutions LLC

Veeraraghavan S Basker

Kangguo Cheng

Junli Wang

Tenko Yamashita

Theodorus E Standaert

Chun-chen Yeh

Ali Khakifirooz

Alexander Reznicek

Zuoguang Liu

Ruilong Xie

Shogo Mochizuki

Andrew Mark Greene

Effendi Leobandung

Oleg Gluschenkov

Huiming Bu

Charles W Koburger, Iii

Julien Frougier

Juntao Li

Sivananda K Kanakasabapathy

Bruce Bennett Doris

Johnathan E Faltermeier

Nicolas J Loubet

Dechao Guo

Reinaldo Ariel Vega

Pouya Hashemi

Toshiharu Furukawa

Hemanth Jagannathan

Hariklia Deligianni

Praneet Adusumilli

Chung-Hsun Lin

William R Tonti

Andres Bryant

Vamsi Krishna Paruchuri

Chun-Chen Yeh

David V Horak

Wilfried Haensch

Pranita Kerber

Rajarao Jammy

Huimei Zhou

Carl John Radens

Hui Zang

Terence B Hook

Jingyun Zhang

Christopher J Penny

Robert Russell Robison

Henry K Utomo

Takashi Ando

Steven J Holmes

Xin Miao

Chanro Park

Keith E Fogel

Shom Ponoth

Su Chen Fan

Guillaume Bouche

Balasubramanian S Haran

Emre Alptekin

Dieter F Wendel

Byeong Yeol Kim

Xinhui Wang

Chih-Chao Yang

Lawrence Alfred Clevenger

Mark Charles Hakey

Balasubramanian Pranatharthiharan

Lars W Liebmann

Cyril Cabral, Jr

Qing Liu

Katherine Lynn Saenger

Dominic Joseph Schepis

Sanjay C Mehta

Martin Michael Frank

Thomas N Adam

Ravikumar Ramachandran

John Michael Cotte

Eduard Albert Cartier

Kisik Choi

Brian Joseph Greene

Richard Quimby Williams

Emanuel Israel Cooper

Haigou Huang

Ramachandra Divakaruni

Keith Kwong Hon Wong

Ruqiang Bao

Zhenxing Bi

Soon-Cheon Seo

Heng Wu

Kern Rim

Jeffrey Bowman Johnson

Laertis Economikos

Babar Ali Khan

Lubomyr Taras Romankiw

Pranita Kulkarni

Xuefeng Liu

Joshua M Rubin

Eric R Miller

Albert Manhee Chu

Anthony I Chou

Indira P Seshadri

Viraj Yashawant Sardesai

Vimal Kumar Kamineni

Lan Yu

Embodiments of the present invention are directed to processing methods and resulting structures for co-integrating gate-all-around (GAA) nanosheets and comb-nanosheets on the same chip, wafer, or substrate. In a non-limiting embodiment of the invention, a GAA nanosheet device is formed in a first region of a substrate. The GAA nanosheet device includes a first nanosheet stack, a second nanosheet stack, and a first fin spacing distance between the first nanosheet stack and the second nanosheet stack. A comb-nanosheet device is formed in a second region of a substrate. The comb-nanosheet device includes a third nanosheet stack, a fourth nanosheet stack, and a second fin spacing distance between the third nanosheet stack and the fourth nanosheet stack that is less than the first fin spacing distance.

Co-integrating gate-all-around nanosheet transistors and comb-nanosheet transistors

FinFET devices and processes to prevent fin or gate collapse (e.g., flopover) in finFET devices are provided. The method includes forming a first set of trenches in a semiconductor material and filling the first set of trenches with insulator material. The method further includes forming a second set of trenches in the semiconductor material, alternating with the first set of trenches that are filled. The second set of trenches form semiconductor structures which have a dimension of fin structures. The method further includes filling the second set of trenches with insulator material. The method further includes recessing the insulator material within the first set of trenches and the second set of trenches to form the fin structures.

FinFET devices

A method of fabricating a static random-access memory (SRAM) device includes forming a sacrificial material and replacing the sacrificial material with a metal to form a cross-couple contact on a metal gate stack. A portion of the metal gate stack directly contacts each of a sidewall and an endwall of the cross-couple contact.

Replacement gate cross-couple for static random-access memory scaling

A semiconductor structure may include one or more nanosheet field-effect transistors formed on a first portion of a substrate, and one or more fin field-effect transistors formed on a second portion of the substrate. A source drain of the one or more nanosheet field-effect transistors or a gate of the one or more nanosheet field-effect transistors may be separated from the substrate by an isolation layer. A source drain of the one or more fin field-effect transistors or a gate of the one or more fin field-effect transistors may be in direct contact with the substrate. The semiconductor structure may include a gate spacer surrounding the gate of the one or more nanosheet field-effect transistors and the gate of the one or more fin field-effect transistors.

Gate-all-around nanosheet field effect transistor integrated with fin field effect transistor

Embodiments are disclosed for a system. The system includes a semiconductor structure. The semiconductor structure includes a dielectric liner that wraps around a top and one side of a substrate island. The dielectric liner separates a substrate from a gate stack. Further, the system includes an access trench in physical contact with the dielectric liner.

Late replacement bottom isolation for nanosheet devices

A semiconductor structure includes a first set of fins and a second set of fins, a dielectric pillar disposed between the first set of fins and the second set of fins, a bottom source/drain (S/D) region directly contacting a bottom surface of the first and second set of fins, and a top S/D region directly contacting a top surface of the first and second set of fins. A high-k metal gate (HKMG) is disposed between fins of the first set of fins and between fins of the second set of fins. The HKMG directly contacts sidewalls of the dielectric pillar. A width of the HKMG between the first set of fins is equal to a width of the HKMG between the second set of fins.

Vertical FET replacement gate formation with variable fin pitch

A semiconductor device fabricated by forming FET fins from a layered semiconductor structure. The layered semiconductor structure incudes a sacrificial layer. Further by forming dummy gate structures on the FET fins, recessing the FET fins between dummy gate structures, growing source-drain regions between FET fins and the sacrificial layer, replacing active region dummy gate structures with high-k metal gates structures, and replacing the sacrificial layer with a dielectric isolation material, wherein the dielectric isolation material extends across the active region.

Field effect transistors with bottom dielectric isolation

In one embodiment a semiconductor structure comprises a semiconductor substrate, a trench dielectric layer disposed in a trench of the semiconductor substrate, a first source/drain region disposed in contact with the semiconductor substrate, a gate and a second source/drain region. The gate is disposed between the first source/drain region and the second source/drain region. The semiconductor structure further comprises a dielectric isolation layer disposed between the semiconductor substrate and the second source/drain region.

Electrostatic discharge diode having dielectric isolation layer

A method of forming a semiconductor device that includes forming a fin structure from a bulk semiconductor substrate and forming an isolation region contacting a lower portion of a sidewall of the fin structure, wherein an upper portion of the sidewall of the fin structure is exposed. A sacrificial spacer is formed on the upper portion of the sidewall of the fin structure. The isolation regions are recessed to provide an exposed section of the sidewall of the fin structure. A doped semiconductor material is formed on the exposed section of the lower portion of the sidewall of the fin structure. Dopant is diffused from the doped semiconductor material to a base portion of the fin structure.

Punch through stopper in bulk finFET device

A semiconductor device includes a semiconductor substrate, a first pair of FET (field effect transistor) gate structures separated by a first gate canyon having a first gate canyon spacing, disposed upon the semiconductor substrate, a second pair of FET gate structures separated by a second gate canyon having a second gate canyon spacing, disposed upon the substrate, a first S/D (source/drain region disposed in the first gate canyon, a second S/D region disposed in the second gate canyon, a first BDI (bottom dielectric isolation) element disposed below the first S/D region and having a first BDI thickness, and a second BDI element disposed below the second S/D region and having a second BDI thickness. The first BDI thickness exceeds the second BDI thickness.

Gate-all-around field effect transistor with bottom dielectric isolation

A method is presented for forming a wrap around contact. The method includes forming a p-type epitaxial region and an n-type epitaxial region over a substrate, forming a dielectric pillar between the p-type epitaxial region and the n-type epitaxial region, depositing sacrificial liners around both the p-type epitaxial region and the n-type epitaxial region, and depositing an inter-layer dielectric (ILD). The method further includes forming trenches in the ILD extending into the sacrificial liners, wherein the trenches are vertically aligned with the p-type epitaxial region and the n-type epitaxial region, removing the sacrificial liners to define irregular-shaped openings exposing the p-type epitaxial region and the n-type epitaxial region, and filling the irregular-shaped openings with a conductive material defining the wrap around contact.

Wrap around contact process margin improvement with early contact cut

A semiconductor structure comprises a substrate having a first side and a second side opposite the first side, and a gate for at least one transistor device disposed above the first side of the substrate. The structure may further include a buried power rail at least partially disposed in the substrate and a gate tie-down contact connecting the gate to the buried power rail from the second side of the substrate. The structure may further or alternatively include one or more source/drain regions disposed over the first side of the substrate, and a gate contact connecting to a portion of the gate from the second side of the substrate, the portion of the gate being adjacent to at least one of the one or more source/drain regions.

Semiconductor structures with backside gate contacts

A semiconductor device including a nanosheet field effect transistor (FET) comprising a thin gate oxide layer and a floating gate memory cell comprising a tunneling oxide, a floating gate, and a blocking oxide layer over a fin FET device. The device fabricated by forming a nanosheet stack and fin structures, forming tunneling oxide and floating gate layers over the nanosheet stack and fin structures, forming dummy gate structures over the nanosheet stack and fin structures, removing the dummy gate structures, forming a blocking oxide layer over the floating gate, and forming replacement metal gates.

Integrated nanosheet field effect transistors and floating gate memory cells

Semiconductor devices and methods of forming the same include recessing sacrificial layers in a stack of alternating sacrificial layers and channel layers using a first etch to form curved recesses at sidewalls of each sacrificial layer in the stack, with tails of sacrificial material being present at a top and bottom of each curved recess. Dielectric plugs are formed that each partially fill a respective curved recess, leaving exposed at least a portion of each tail of sacrificial material. The tails of sacrificial material are etched back using a second etch to expand the recesses. Inner spacers are formed in the expanded recesses.

Dual step etch-back inner spacer formation

An apparatus comprising a substrate and a thin gate oxide nanosheet device located on the substrate, having a first plurality of nanosheet layers, wherein each of the first plurality of nanosheet layers has a first thickness located at the center of the nanosheet. A thick gate oxide nanosheet device located on the substrate, having a second plurality of nanosheet layers, wherein each of the second plurality of nanosheet layers has a second thickness and wherein the first thickness is less than the second thickness.

Thick gate oxide device option for nanosheet device

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Schenectady, NY, United States of America

Veeraraghavan S Basker