Altera Corporation

Intel Corporation

Vasudeva M Kamath

Mahesh A Iyer

Robert L Walker

Configuration data for an integrated circuit may be generated using logic design equipment to implement a logic design on the integrated circuit. The equipment may perform multiple rounds of incremental physical synthesis, incremental timing analysis, and incremental legalization operations. Each round may involve performing multiple different physical synthesis transforms on the design that are individually rejected until transforms that satisfy legality constraints and improve timing for the logic design are found and incorporated into the netlist. The configuration data may then be generated using the netlist. In this way, the logic design may be incrementally altered and verified during the physical synthesis process. This prevents the need for rejecting or accepting an entire batch logic changes to the netlist even when only some of the changes are non-ideal, thus optimizing circuit performance as well as the compile time required to implement the logic design on the integrated circuit.

Methods for incremental circuit physical synthesis

A method for designing a system on a target device includes performing register retiming on an original design for the system to generate a retimed design. The retimed design is verified to determine whether it is structurally correct by performing a plurality of iterations of register retiming on the retimed design, wherein each iteration accounts for the register retiming of registers in the system driven by a different clock.

Method and apparatus for performing rewind structural verification of retimed circuits driven by a plurality of clocks

A method for performing a rewind functional verification includes identifying state variables that model a number of registers on each edge of a retiming graph for an original design and a retimed design. Random variables are identified that model retiming labels representing a number and a direction of a register movement relative to a node on a retiming graph for the retimed design. A retiming constraint is identified for each edge on the retiming graph for the retimed design, wherein the retiming constraint reflects a relationship between the state variables and the random variables. A random variable that models a retiming label at a source of an edge is recursively substituted for a random variable that models a retiming label at a sink of the edge when a number of registers on the edge is unchanged after register retiming.

Method and apparatus for reducing constraints during rewind structural verification of retimed circuits

A computer-implemented method includes performing retiming using a circuit design to determine a retimed variation to the circuit design. The circuit design includes a first set of registers with defined power-up states and the variations each comprise a second set of registers that correspond to the first set of registers. The method includes maintaining fixed power-up states for the second set of registers in the variations. The fixed power-up states for the second set of registers are equivalent to the defined power-up states of the first set of registers. The method includes identifying registers of the second set of registers involved in an initial state conflict, and performing a mitigating action to resolve the initial state conflict to enable retiming to continue while maintaining functionally equivalent behavior as the circuit design. Various choices of initial states are also explored during retiming to increase the effect of retiming.

Retiming with fixed power-up states

A computer-implemented includes performing retiming using a circuit design to determine variation to the circuit design. The circuit design includes a first set of registers with defined power-up states and the variations each comprise a second set of registers that correspond to the first set of registers. The method includes computing and maintaining programmable power-up states for the second set of registers in the variations. The programmable power-up states computed for the second set of registers are equivalent to the defined power-up states of the first set of registers. The method includes identifying registers of the second set of registers involved in an initial state conflict, and performing a mitigating action to resolve the initial state conflict to enable retiming to continue while maintaining functionally equivalent behavior as the circuit design. Various choices of initial states are also explored during retiming to maximize the effect of retiming.

Retiming with programmable power-up states

An integrated circuit design may include registers and combinational logic. Integrated circuit design computing equipment may perform register retiming in the circuit design, whereby registers are moved across one or more portions of the combinational logic. The candidate registers to be retimed may have a different number or different types of secondary signals. In such scenarios, a selective modeling operation may be performed according to a predetermined precedence scheme to remove and model the differing secondary signals, thereby producing comparable registers with the same number and type of secondary signals. The comparable registers can then be retimed across the corresponding combinational logic. Backward or forward retiming operations may be performed in this way to achieve optimal circuit performance. During retiming adjacent combinational logic may also be combined to help minimize circuit area.

Integrated circuit retiming with selective modeling of flip-flop secondary signals

A method for designing a system on a target device includes performing register retiming on an original design for the system to generate a retimed design. The retimed design is verified to determine whether it is structurally correct by performing a plurality of iterations of register retiming on the retimed design, wherein each iteration accounts for the retiming of registers in the system driven by a different clock.

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San Jose, CA, United States of America

Vasudeva M Kamath