Micron Technology Incorporated

Nan Ya Technology Corporation

Vassil N Antonov

Vishwanath Bhat

Chris M Carlson

Tsai-Yu Huang

Manuj Nahar

Jeffery B Hull

Hung-Wei Liu

Albert Liao

Christopher W Petz

Matthew N Rocklein

Darwin Franseda Fan

Chun-I Hsieh

Bhaskar Srinivasan

Anish A Khandekar

Dan Gealy

Ashonita A Chavan

Irina V Vasilyeva

Masihhur R Laskar

Nik Mirin

Xue-Feng Lin

Durai Vishak Nirmal Ramaswamy

Kamal M Karda

John A Smythe

Prashant Raghu

Joseph Neil Greeley

Qian Tao

Jaydeb Goswami

Michael Mutch

Zhe Song

Sanket S Kelkar

Paul A Paduano

Duane M Goodner

Clement Jacob

Jennifer K Sigman

Chun I Hsieh

Ali Moballegh

Kotha Sai Madhukar Reddy

Wei Hui Hsu

A DRAM capacitor comprising a first capacitor electrode configured as a container and comprising a doped titanium nitride material, a capacitor dielectric on the first capacitor electrode, and a second capacitor electrode on the capacitor dielectric. Methods of forming the DRAM capacitor are also disclosed, as are semiconductor devices and systems comprising such DRAM capacitors.

Doped titanium nitride materials for dram capacitors, and related semiconductor devices

A method of forming a vertical transistor comprising a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region comprises, in multiple time-spaced microwave annealing steps, microwave annealing at least the channel region. The multiple time-spaced microwave annealing steps reduce average concentration of elemental-form H in the channel region from what it was before start of the multiple time-spaced microwave annealing steps. The reduced average concentration of elemental-form H is 0.005 to less than 1 atomic percent. Structure embodiments are disclosed.

Vertical transistor, integrated circuitry, method of forming a vertical transistor, and method of forming integrated circuitry

A transistor comprises a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region. The channel region is crystalline and comprises a plurality of vertically-elongated crystal grains that individually are directly against both of the top source/drain region and the bottom source/drain region. Other embodiments, including methods, are disclosed.

Vertical transistors having at least 50% grain boundaries offset between top and bottom source/drain regions and the channel region that is vertically therebetween

A ferroelectric capacitor comprises two conductive capacitor electrodes having ferroelectric material there-between. At least one of the capacitor electrodes comprise MSiO, where 'M' is at least one of Ru, Ti, Ta, Co, Pt, Ir, Os, Mo, V, W, Sr, Re, Rh, Pd, La, Zn, In, Sig, and Nb, Other aspects, including method, are disclosed.

Ferroelectric capacitor, a ferroelectric memory cell, an array of ferroelectric memory cells, and a method of forming a ferroelectric capacitor

Vertical transistors with channel region having vertically elongated crystal grains that individually are directly against both of the top and bottom source/drain regions

Doped titanium nitride materials for DRAM capacitors, and related semiconductor devices, systems, and methods

A ferroelectric capacitor comprises two conductive capacitor electrodes having ferroelectric material there-between. At least one of the capacitor electrodes comprise MSiO, where 'M' is at least one of Ru, Ti, Ta, Co, Pt, Ir. Os, Mo, V, W, Sr, Re, Rh, Pd, La, Zn, In, Sn, and Nb. Other aspects, including method, are disclosed.

A transistor comprises a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region. An upper material is directly above a lower material. The upper material is in at least one of the top source/drain region, the bottom source/drain region, and the channel region. The lower material is in at least one of the top source/drain region, the bottom source/drain region, and the channel region. The upper material comprises 1 atomic percent to 10 atomic percent elemental-form H and 0 total atomic percent to less than 0.1 total atomic percent of one or more noble elements. The lower material comprises 0 atomic percent to less than 1 atomic percent elemental-form H and 0.1 total atomic percent to 10 total atomic percent of one or more noble elements. Other embodiments, including method, are disclosed.

Transistor and methods of forming transistors

A method used in forming at least a portion of at least one conductive capacitor electrode of a capacitor that comprises a pair of conductive capacitor electrodes having a capacitor insulator there-between comprises forming an insulative first material comprising an amorphous insulative metal oxide. The amorphous insulative metal oxide is reduced in a reducing-ambient to form a conductive second material from the insulative first material. Such reducing in the reducing-ambient both (a) removes oxygen from and changes the stoichiometry of the metal oxide, and (b) crystallizes the metal oxide into a crystalline state that is conductive.

Methods used in forming at least a portion of at least one conductive capacitor electrode of a capacitor that comprises a pair of conductive capacitor electrodes having a capacitor insulator there-between and methods of forming a capacitor

Some embodiments include methods of forming rutile-type titanium oxide. A monolayer of titanium nitride may be formed. The monolayer of titanium nitride may then be oxidized at a temperature less than or equal to about 550&#xb0; C. to convert it into a monolayer of rutile-type titanium oxide. Some embodiments include methods of forming capacitors that have rutile-type titanium oxide dielectric, and that have at least one electrode comprising titanium nitride. Some embodiments include thermally conductive stacks that contain titanium nitride and rutile-type titanium oxide, and some embodiments include methods of forming such stacks.

Constructions comprising rutile-type titanium oxide; and methods of forming and utilizing rutile-type titanium oxide

A method of forming a capacitor includes depositing a dielectric metal oxide layer of a first phase to a thickness no greater than 75 Angstroms over an inner conductive capacitor electrode material. The first phase dielectric metal oxide layer has a k of at least 15. Conductive RuOis deposited over and into physical contact with the dielectric metal oxide layer. Then, the RuOand the dielectric metal oxide layer are annealed at a temperature below 500&#xb0; C. The RuOin physical contact with the dielectric metal oxide during the annealing facilitates a change of the dielectric metal oxide layer from the first phase to a second crystalline phase having a higher k than the first phase. The annealed dielectric metal oxide layer is incorporated into a capacitor dielectric region of a capacitor construction. Other implementations are disclosed.

Methods of forming capacitors

A semiconductor structure may include a first electrode over a substrate, a high-K dielectric material over the first electrode, and a second electrode over the high-K dielectric material, wherein at least one of the first electrode and the second electrode may include a material selected from the group consisting of a molybdenum nitride (MoN) material, a molybdenum oxynitride (MoON) material, a molybdenum oxide (MoO) material, and a molybdenum-based alloy material comprising molybdenum and nitrogen.

Semiconductor structures including molybdenum nitride, molybdenum oxynitride or molybdenum-based alloy material, and method of making such structures

Some embodiments include a method of forming a capacitor. An opening is formed through a silicon-containing mass to a base, and sidewalls of the opening are lined with protective material. A first capacitor electrode is formed within the opening and has sidewalls along the protective material. At least some of the silicon-containing mass is removed with an etch. The protective material protects the first capacitor electrode from being removed by the etch. A second capacitor electrode is formed along the sidewalls of the first capacitor electrode, and is spaced from the first capacitor electrode by capacitor dielectric. Some embodiments include multi-material structures having one or more of aluminum nitride, molybdenum nitride, niobium nitride, niobium oxide, silicon dioxide, tantalum nitride and tantalum oxide. Some embodiments include semiconductor constructions.

Multi-material structures and capacitor-containing semiconductor constructions

Growing community of inventors

Boise, ID, United States of America

Vassil N Antonov