Cypress Semiconductor Corporation

Sandisk Technologies Inc.

Matrix Semiconductor, Inc.

Sandisk 3d LLC

Vani Verma

Bo Soon Chang

Hem P Takiar

Khushrav S Chhor

Cheemen Yu

Anthony Odejar

Cheeman Yu

Annie Tan

A method of fabricating a leadframe-based semiconductor package, and a semiconductor package formed thereby, are disclosed. In embodiments, a semiconductor die having die bond pads along two adjacent edges may be electrically coupled to four sides of a four-sided leadframe. Embodiments relate to lead and no-lead type leadframe.

Two-sided die in a four-sided leadframe based package

Method of fabricating a two-sided die in a four-sided leadframe based package

A multi-chip memory module may be formed including two or more stacked integrated circuits mounted to a substrate or lead frame structure. The memory module may include means to couple one or more of the stacked integrated circuits to edge conductors in a memory card package configuration. Such means may include the capability to utilize bonding pads on all four sides of an integrated circuit. A lead frame structure may be divided into first and second portions. The first portion may be adapted to receive the stacked integrated circuits and the second portion may include a plurality of conductors. The first portion may also be adapted to couple at least one of the integrated circuits to power and ground conductors on the second portion. In one embodiment, the first portion may include the lead frame paddle and a conductive ring. In another embodiment, the first portion may include first and second coplanar elements.

Memory module having interconnected and stacked integrated circuits

An integrated circuit packaging device includes a laminate substrate. A first surface of the substrate can be mounted on an integrated circuit and the second surface can be mounted on a surface of a printed circuit board. The device can also include an array of lead contact pads on the first surface that can provide wire bond connections to circuit contact pads in the integrated circuit, and an array of solder ball contact pads on the second surface. Routing layers can provide electrical coupling between the lead contact pads on the first surface and the solder ball contact pads on the second surface. A dedicated contact pad on the first surface is electrically coupled to the laminate substrate.

Non-stick detection method and mechanism for array molded laminate packages

A method and system for universal packaging in conjunction with an automated in-line back-end IC manufacturing process. In one method embodiment, the present invention processes a die-strip through a number of integrated in-line processes that function independently of the die size of the die-strip. A control computer maintains a die-strip map database recording the die size of the die-strip. In-line molding and solder ball attachment processes are then performed and function independently of the die size of the die-strip. Processes that are independent of die size provide a universal packaging manufacturing solution. The present invention then accesses the database to determine the die size for cutting the die-strip based on specifications maintained by the electronic die-strip map database. Sorting, testing and finish assembly processes are then performed.

Method and system for universal packaging in conjunction with a back-end integrated circuit manufacturing process

Embodiments of the present invention relate to a method and mechanism for testing wire bonds in an integrated circuit package. The method comprises bonding an integrated circuit silicon die to a package substrate. Next, wire connections are formed between pads in the integrated circuit silicon die and contact leads in the package substrate and testing each of the wire connections in order to detect non-stick failures using electrical continuity provided by the integrated circuit silicon die substrate. Electrical continuity is provided through dedicated pads in the package substrate that contact the underside of the silicon die substrate. The dedicated contact pads in each package substrate of the molded laminate array are connected to each other and to the mold gate. The continuity thus provided allows a non-stick-on-pad test by ensuring continuity between the wire spool through the die to the mold gate. Non-stick-on-lead check then looks for an open circuit between the wire spool and the mold gate which indicates a successful wire bond to the lead and associated separation from the wire feed capillary. The IC contact pads and leads in the package substrate are electrically isolated in order to allow functional testing and burn-in while the packaged integrated circuits are still in the laminate substrate array.

A lead frame includes a first side rail, a second side rail spaced apart from the first side rail, a center rail disposed between the first side rail and the second side rail, and a plurality of package locations. Each package location includes a first and a second die attach paddle. The first die attach paddle supports a first side of a semiconductor die and is coupled only to the first side rail or to the second side rail. The second die attach paddle supports a second side of the semiconductor die and is coupled only to the center rail. The first and second die attach paddles are separate and unconnected to each other and may be generally circular in shape. An aggregate surface area of the first and second paddles may be less than about 25 percent of a surface area of the semiconductor die. By limiting the surface area of the interfaces between the lead frame and the silicon die and the surface area of the interfaces between the lead frame and the molding compound, moisture-related problems and problems related to the differing coefficients of thermal expansion (such as delamination and/or cracks, for example) of the constituent materials of the resultant semiconductor device are minimized.

Methods for producing high reliability lead frame and packaging semiconductor die using such lead frame

An apparatus and method for providing delamination-resistant, array type molding of chip laminate packages such that larger chip array block sizes may be employed. An advanced mold die provides multiple wells for the formation of ejector pin tabs to be formed integrally to the mold cap of a chip laminate package. The die further provides for an ejector pin hole to be located at each ejector pin tab such that the ejector pins, when pressed for release of the laminate package from the mold die, bear against the integrally formed pin tabs rather than against the substrate of the chip/substrate assembly. The placement of the ejector pins for bearing against the pin tabs precludes the loading of the interface within the laminate package between the mold cap and the chip/substrate assembly. Substantially reduced delamination of the chip laminate package is achieved allowing for the use of larger chip array block sizes and providing for a substantial reduction in chip laminate package moisture sensitivity.

Growing community of inventors

Sunnyvale, CA, United States of America

Vani Verma