Applied Materials, Inc.

Vanessa Pena

Naomi Yoshida

Shiyu Sun

Nam Sung Kim

Michael Patrick Chudzik

Errol Antonio C Sanchez

Benjamin Colombeau

Theresa Kramer Guarini

Bingxi Sun Wood

Sung Won Jun

Ellie Y Yieh

Mehul B Naik

Mikhail Korolik

John Tolle

Seshadri Ramaswami

Lin Dong

Dimitri R Kioussis

Myungsun Kim

Thomas Kirschenheiter

Andrew Cockburn

Gaetano Santoro

Daniel Philippe Cellier

Wei Hong

Embodiments of the disclosure advantageously provide semiconductor devices CFET in particular and methods of manufacturing such devices having a fully strained superlattice structure with channel layers that are substantially free of defects and release layers having a reduced selective removal rate. The CFET described herein comprise a vertically stacked superlattice structure on a substrate, the vertically stacked superlattice structure comprising: a first hGAA structure on the substrate; a sacrificial layer on a top surface of the first hGAA structure, the sacrificial layer comprising silicon germanium (SiGe) having a germanium content in a range of from greater than 0% to 50% on an atomic basis; and a second hGAA structure on a top surface of the sacrificial layer. Each of the first hGAA and the second hGAA comprise alternating layers of nanosheet channel layer that comprise silicon (Si) and nanosheet release layer that comprise doped silicon germanium (SiGe).

Monolithic complementary field-effect transistors having carbon-doped release layers

Embodiments described herein generally relate to methods and device structures for horizontal gate all around (hGAA) isolation and fin field effect transistor (FinFET) isolation. A superlattice structure comprising different materials arranged in an alternatingly stacked formation may be formed on a substrate. In one embodiment, at least one of the layers of the superlattice structure may be oxidized to form a buried oxide layer adjacent the substrate.

Horizontal gate all around and FinFET device isolation

The present disclosure provides methods for forming horizontal gate-all-around (hGAA) structure devices. In one example, a method includes selectively and laterally etching a first group of sidewalls of a first layer in a multi-material layer, wherein the multi-material layer comprises repeating pairs of the first layer and a second layer, the first and the second layers having the first group and a second group of sidewalls respectively, the first group of sidewalls from the first layer exposed through openings defined in the multi-material layer and a group of inner spacers formed atop of the second group of sidewalls from the second layer, forming a recess from the first group of sidewalls of the first layer and defining a vertical wall inward from an outer vertical surface of the inner spacer formed atop of the second layers, and forming an epi-silicon layer from the recess of the first layer.

Method for fabricating junctions and spacers for horizontal gate all around devices

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Flemish Brabant, Belgium

Vanessa Pena