Globalfoundries Singapore Pte. Ltd.

Valerio Perez

Ushasree Katakamsetty

Wee Kwong Yeo

Shyue Fong Quek

Chiu Wing Hui

Yang Qing

Enhancements in lithography for forming an integrated circuit are disclosed. The enhancements include a topography analysis of a design data file to obtain accumulative topography information for different mask levels. The topography information facilitates topography driven optical proximity correction and topography driven lithography.

Topography driven OPC and lithography flow

A design or lithographic enhancement process, a method for forming a device based on the lithographic enhancement process and a system for pattern enhancement are presented. The process includes processing a design data file. The design data file includes information of design layers in an integrated circuit (IC). Processing the design data file includes analyzing the design data file and patterns in the design data file are enhanced taken into consideration topography information of design layers corresponding to masks of the IC.

Growing community of inventors

Singapore, Singapore

Valerio Perez