Commissariat a L'energie Atomique Et Aux Energies Alternatives

Weebit Nano Ltd.

Commissariat À L'énergie Atomique Et Aux Énergies Alternatives

Valentin Gherman

Samuel Evain

Bastien Giraud

Yannick Bonhomme

Ilan Sever

Marcelino Seif

Sebastien Ricavy

Cyrille Laffond

Sébastien Ricavy

A solution for improving the correction of errors in a 2T2R resistive memory protected by an error correction code. A method that makes it possible, through 1T1R read operations, to identify, in a codeword stored in memory, bits liable to be incorrect, called 'erasures', and then to invert these bits in the stored codeword in order to generate a new word corrected by the ECC.

Method and device for correcting errors in resistive memories

A method is provided for writing a data word to a resistive memory consisting of 2T2R differential cells each having first and second sets of a resistor (R) and a selection transistor (T). The method includes generating an initial codeword, programming it in 1T1R mode, checking its programming in 1T1R mode, inverting it, programming the inverted initial codeword in 1T1R mode, checking its programming in 1T1R mode, and reading, in 2T2R differential mode, that the read data correspond to said initial data. A device designed to implement this write method and to an electronic system including this device is also provided.

Write method for differential resistive memories

An electroforming process for a resistive memory of a memory device including a memory controller, an encoder computing an inversion-invariant linear error correction code, and a write device connected directly to the encoder. An electroforming device performing electroforming through write operations to such a resistive memory and to a method for checking a write operation.

Electroforming process using an inversion-invariant linear ECC, and associated device

A method for selectively inverting a word to be written to a memory is provided. The memory includes memory cells, each memory cell allowing at least two values associated with at least one bit to be stored, the decision as to whether to invert a word being made depending on a number of vulnerable values, which number is determined on the basis of the data bits, of the inversion bit and of uneven check bits.

Method for selectively inverting words to be written to a memory and device for implementing same

A method for controlling the refresh of data in reprogrammable nonvolatile memories includes a plurality of memory pages for storing data. The method performs the steps of: identifying with an error correction code errors in a read memory page; computing among the identified errors the number of retention errors and of non-retention errors, the non-retention errors especially comprising repeated read or programming errors; computing the retention age of the read memory page; estimating the remaining retention time for the read memory page depending on the parameters number of retention errors, number of non-retention errors and retention age computed beforehand; comparing the estimated value of the remaining retention time to a predefined value corresponding to a maximum time interval between two successive operations of reading a memory page; and determining whether the read memory page must be refreshed or not depending on the results of the comparison determining whether the page must be refreshed or not depending on the estimated value of the remaining retention time.

Device and method for controlling the data refresh cycles in reprogrammable non-volatile memories

A device for controlling the refresh cycles of data stored in a non-volatile memory is provided. The device comprises a temperature sensor capable of measuring the temperature of at least one non-volatile memory and of delivering information representing the measured temperature, and a control module coupled to the temperature sensor capable of using the temperature information with modelling of the impact of the temperature on the retention time of the data in order to determine whether a loss of data is imminent and, if so, in order to generate an alarm.

Device and method for controlling refresh cycles of non-volatile memories

A method is provided for generating a maximized linear correcting code from a base linear correcting code, the base correcting code and the maximized linear correcting code being associated with one and the same parity matrix H, the matrix being used to generate syndromes, the syndromes being used for decoding code words. The method comprises a step of identifying the syndromes unused for decoding the base linear correcting code, a step of identifying the errors that can affect the code words and make it possible to obtain the unused syndromes when a code word is multiplied by the matrix H and a step of selecting a unique error for each unused syndrome from among the identified errors, the error being called additional error.

Method for generating a maximized linear correcting code, method and device for decoding such a code

A device for correcting an initial binary word affected by an error in 1 or 2 bits and arising from a corrector code endowed with a minimum Hamming distance of 3 or 4, comprises first means for correcting an error of 1 bit and for detecting an error of more than 1 bit in the initial word and second means for correcting an error of 1 bit in a word arising from an inversion module, able to receive a datum indicative of a binary level of confidence, low or high, assigned to each of the bits of at least one part of the initial word, said inversion module being configured to invert the bits of the initial word which suffer the low confidence level, and a multiplexer with at least two inputs which is driven by the means for detecting an error of more than 1 bit in the initial word, said multiplexer being fed on a first input by the output of the first correction means and on a second input by the output of the second correction means.

Device for correcting two errors with a code of hamming distance three or four

A device for monitoring the latency of electronic circuits based on microtechnology and/or nanotechnology, said circuits to be tested being supplied with the aid of a voltage Vdd, having a low level and a high level, for the detection of delay faults of said circuits, comprises: at least one device of type I placed between the high level of the power supply voltage and the elements of the circuit to be tested, and/or at least one device of type II placed between the low level of the power supply voltage of the elements of the elements of said circuit to be tested, the device of type I and the device of type II comprising at least one low-latency electrical path, said low-latency path being connected in parallel with a high-latency electrical path, a test signal monitoring the opening of the low-latency paths while the high-latency electrical paths are open.

Method and device for controlling the latency of electronic circuits

A method for online testing pipeline systems comprising a succession of stages separated by buffers each associated with an idle signal, or idle signal, and/or at least one status bit, comprising: detecting values of the idle signal and/or the corresponding status bits indicating the availability of a cycle or the abrupt interruption of the flow of operations in a pipeline, and indicating that a valid operation, executed by a stage in the pipeline, is followed by an unused cycle; maintaining the state of the buffer in order to allow said valid operation to be re-executed during the unused cycle indicated by said idle signal; re-executing, during the unused cycle, the valid operation, in order to obtain at least a first version and a second version of said valid operation; memorizing, at the output of the pipeline, the results that correspond to the first version of said repeated or re-executed operation, in order to compare with the results of said second version of the same repeated or re-executed operation; and comparing the results obtained at the output of the pipeline, which results correspond to the first version and the second version, and, if there is a difference, indicating an error.

Method for the on-line testing of pipeline stages temporarily not in use, and associated device

An error-correcting coding method generates code words of m bits from useful data blocks of n bits. The method adds k check bits to a block of n useful data bits in order to generate a code word of m=n+k bits, said check bits being defined according to the combination rules defined by a parity matrix H consisting of binary elements and having k rows and m columns such that H&#xb7;V=0, V being a column matrix whose m elements are the m bits of the code word to be generated. The k check bits are separated into two groups, on the one hand a group of k1 bits called total parity bits PT and on the other hand a group of k2 bits called conventional check bits VC, the values of k, k1 and k2 satisfying the conditions k=k1+k2 and k&#x3e;k1&#x3e;2, the matrix H whose columns can be swapped being broken down into six submatrices A, B, C, D, E and F. Another method detects multiple errors in code words generated by the coding method.

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Palaiseau, France

Valentin Gherman