Infineon Technologies Ag

Uwe Schilling

Matthias Lehr

Dietmar Temmler

Martin Popp

Stephan Wege

Zvonimir Gabric

Markus M Kirchhoff

Oswald Spindler

Kristin Schupke

Veronika Polei

Hans-Peter Sperlich

Irene Sperl

Kerstin Pomplun

Hans Glawischnig

A semiconductor component has a cavity formed in a monocrystalline silicon substrate. The wall of the cavity is covered by a cover layer, at least in an upper collar region, and a covering layer is then applied to the surface of the silicon substrate using a selective epitaxial growth method. The cavity is thereby covered in the process. The method is physically simple and can be carried out cost-effectively. In particular, the described method can be used in order to cover a trench prior to high-temperature processes during the production of a DRAM memory, and to open the trench once again after the high-temperature processes, in order to provide a trench capacitor.

Method for producing a cavity in a monocrystalline silicon substrate and a semiconductor component having a cavity in a monocrystalline silicon substrate with an epitaxial covering layer

A method for producing antifuse structures and antifuses by which adjacent conductive regions can be selectively electrically connected involve the application of a sacrificial layer to a first conductive region. The sacrificial layer is patterned with the aid of a photolithographic method. A fuse layer is applied and the sacrificial layer is then removed. A non-conductive layer is applied and a conductive material is introduced in an opening in the non-conductive layer for the purpose of forming a second conductive region.

Method for producing an antifuse and antifuse for the selective electrical connection of adjacent conductive regions

A process for fabricating a semiconductor component includes providing a trench in a substrate and depositing a liner layer on the resulting structure using a nonconformal deposition process. This results in the liner layer being significantly smaller at the trench walls and base than on the substrate surface. An insulating layer is provided on the resulting structure by a conformal deposition process. The insulating layer is then anisotropically etched to remove the insulating layer from a region of the trench base.

Fabrication process for a semiconductor component

A method for the shrink-hole-free filling of trenches in semiconductor circuits which utilizes selective growth of a layer to be applied is described. In the method, a layer of a selective growing material is applied simultaneously to a growth-promoting layer and to a growth-inhibiting layer. Wherein raised portions which, before the layer of selective growing material is applied, are covered by the growth-inhibiting layer at least on their sides. After the growth-inhibiting layer has been applied, the growth-promoting layer is generated by anisotropic treatment on surfaces parallel to the substrate on and between the raised portions and the layer is then removed again on surfaces parallel to the substrate on the raised portions. The method makes it possible to produce in a particularly simple manner a pattern on the raised portions of which are covered by the growth-inhibiting layer on their sides and on their top whereas the bottom of trenches is covered with a growth-promoting layer.

Deposition of various base layers for selective layer growth in semiconductor production

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Dresden, Germany

Uwe Schilling