Suvolta, Inc.

Mie Fujitsu Semiconductor Limited

Avago Technologies General IP (singapore) Pte. Ltd.

Urupattur C Sridharan

Pushkar Ranade

Dalong Zhao

Lance A Scudder

Charles Stager

Lance S Scudder

Taiji Ema

John Dwight Larson, Iii

Scott E Thompson

John Choy

Kevin J Grannen

Thomas Hoffmann

Teymur Bakhishev

Kazushi Fujita

Mitsuaki Hori

Paul E Gregory

Michael Duane

Junji Oh

Donald Lee

Yasunobu Torii

Hongjun Feng

Carrie A Rogers

Toshifumi Mori

A method for fabricating field effect transistors using carbon doped silicon layers to substantially reduce the diffusion of a doped screen layer formed below a substantially undoped channel layer includes forming an in-situ epitaxial carbon doped silicon substrate that is doped to form the screen layer in the carbon doped silicon substrate and forming the substantially undoped silicon layer above the carbon doped silicon substrate. The method may include implanting carbon below the screen layer and forming a thin layer of in-situ epitaxial carbon doped silicon above the screen layer. The screen layer may be formed either in a silicon substrate layer or the carbon doped silicon substrate.

Reducing or eliminating pre-amorphization in transistor manufacture

Methods for fabricating semiconductor devices and devices therefrom are provided. A method includes providing a substrate having a semiconducting surface with first and second layers, where the semiconducting surface has a plurality of active regions comprising first and second active regions. In the first active region, the first layer is an undoped layer and the second layer is a highly doped screening layer. The method also includes removing a part of the first layer to reduce a thickness of the substantially undoped layer for at least a portion of the first active region without a corresponding thickness reduction of the first layer in the second active region. The method additionally includes forming semiconductor devices in the plurality of active regions. In the method, the part of the first layer removed is selected based on a threshold voltage adjustment required for the substrate in the portion of the first active region.

CMOS structures and processes based on selective thinning

Silicon loss prevention in a substrate during transistor device element manufacture is achieved by limiting a number of photoresist mask and chemical oxide layer stripping opportunities during the fabrication process. This can be achieved through the use of a protective layer that remains on the substrate during formation and stripping of photoresist masks used in identifying the implant areas into the substrate. In addition, undesirable reworking steps due to photoresist mask misalignment are eliminated or otherwise have no effect on consuming silicon from the substrate during fabrication of device elements. In this manner, device elements with the same operating characteristics and performance can be consistently made from lot to lot.

Method for substrate preservation during transistor fabrication

The temperature-compensated film bulk acoustic resonator (FBAR) device comprises an FBAR stack that comprises an FBAR characterized by a resonant frequency having a temperature coefficient and a temperature-compensating layer comprising doped silicon dioxide. The FBAR comprises opposed planar electrodes and a piezoelectric element between the electrodes. The piezoelectric element has a temperature coefficient on which the temperature coefficient of the resonant frequency of the FBAR depends at least in part.

Film bulk acoustic resonator (FBAR) devices with temperature compensation

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San Jose, CA, United States of America

Urupattur C Sridharan