International Business Machines Corporation

Globalfoundries Inc.

Globalfoundries U.S. 2 LLC

Freescale Semiconductor,inc.

Unoh Kwon

Siddarth A Krishnan

Vijay Narayanan

Takashi Ando

Michael Patrick Chudzik

Ruqiang Bao

Balaji Kannan

Keith Kwong Hon Wong

Ravikumar Ramachandran

Shahab Siddiqui

Aritra Dasgupta

William K Henson

Rekha Rajaram

Dechao Guo

Zhengwen O Li

Jeffrey W Sleight

Rishikesh Krishnan

Wing L Lai

Sean M Polvino

Oleg Gluschenkov

Ramachandra Divakaruni

Hemanth Jagannathan

Changhwan Choi

Carl John Radens

Reinaldo Ariel Vega

Richard Stephan Wise

Ramachandran Muralidhar

Emre Alptekin

Naim Moumen

Yue Liang

James Kenyon Schaeffer, Iii

Kai Zhao

Dureseti Chidambarrao

Martin Michael Frank

Shreesh Narasimha

Andrew Herbert Simon

Brian Joseph Greene

Huiming Bu

Rajasekhar Venigalla

Wesley Charles Natzle

Viorel C Ontalus

Michael P Belyansky

Nicolas L Breil

Joseph Francis Shepard, Jr

Xiaojun Yu

Min Dai

Charlotte DeWan Adams

Filippos Papadatos

Wei He

Chun-chen Yeh

Judson Robert Holt

Christian Lavoie

Arvind Kumar

Zhen Zhang

Eduard Albert Cartier

John Anthony Fitzsimmons

Yun-Yu Wang

Henry K Utomo

Viraj Yashawant Sardesai

Hongwen Yan

Oh-Jung Kwon

Christopher Carr Parks

Cung D Tran

Hari V Mallela

Michael Vincent Aquilino

Christopher D Sheraw

Sameer Hemchand Jain

Daewon Yang

Rashmi Jha

Dong-Ick Lee

Shahrukh Akbar Khan

Huihang Dong

Massud A Aminpur

Youngjin Choi

Ayse M Ozbek

Dimitri Anastassios Levedakis

Embodiments of the invention include a wafer having gate stacks over channel fins. The wafer includes a first channel fin in an n-type region of a substrate, a second channel fin in a p-type region of the substrate, and a gate dielectric over the substrate and the first and second channel fins. A work function metal stack is over the gate dielectric, the first channel fin in the n-type region, and the second channel fin in the p-type region. The work function metal stack over the gate dielectric and the first channel fin in the n-type region forms a first work function metal stack. The work function metal stack over the gate dielectric and the second fin in the p-type region forms a second work function metal stack. The first work function metal stack includes a shared layer of work function metal shared with the second work function metal stack.

Gate formation scheme for n-type and p-type transistors having separately tuned threshold voltages

Embodiments of the invention are directed to a method that includes forming a first channel fin in an n-type region of a substrate, forming a second channel fin in a p-type region of the substrate, and depositing a gate dielectric over the substrate and the first and second channel fins. A work function metal stack is deposited over the gate dielectric, the first fin in the n-type region, and the second fin in the p-type region. The work function metal stack over the gate dielectric and the first fin in the n-type region forms a first work function metal stack. The work function metal stack over the gate dielectric and the second fin in the p-type region forms a second work function metal stack. The first work function metal stack includes at least one shared layer of work function metal that is shared with the second work function metal stack.

Semiconductor devices include at least one semiconductor fin in each of a first region and a second region. A first work function stack includes a bottom layer and a middle layer formed over the at least one semiconductor fin in the first region. A second work function stack includes a first layer and a second layer formed over the at least one semiconductor fin in the second region. The first layer is continuous with the bottom layer of the first work function stack and the second layer is continuous with the middle layer of the first work function stack, but has a smaller thickness than the middle layer.

Shared metal gate stack with tunable work function

A method for forming a replacement metal gate structure sharing a single work function metal for both the N-FET and the P-FET gates. The method oppositely dopes a high-k material of the N-FET and P-FET gate, respectively, using a single lithography step. The doping allows use of a single work function metal which in turn provides more space in the metal gate opening so that a bulk fill material may occupy more volume of the opening resulting in a lower resistance gate.

Methods and structure to form high K metal gate stack with single work-function metal

The disclosure relates to semiconductor structures and, more particularly, to structures with thinned dielectric material and methods of manufacture. The method includes depositing a high-k dielectric on a substrate. The method further includes depositing a titanium nitride film directly on the high-k while simultaneously etching the high-k dielectric.

Structures with thinned dielectric material

A semiconductor device includes a first transistor formed on a substrate, the first transistor including a channel region positioned on the substrate; a second transistor formed on the substrate, the second transistor including a channel region positioned on the substrate; a high-k dielectric layer disposed on the channel region of the first transistor and the channel region of the second transistor; a first transistor metal gate positioned in contact with the high-k dielectric on the first transistor; a second transistor metal gate positioned in contact with the high-k dielectric on the second transistor; an oxygen absorbing barrier disposed in contact with the high-k dielectric between the first transistor and the second transistor; and a conductive electrode material disposed on the first transistor, the second transistor, and the oxygen absorbing barrier.

Structure and method to suppress work function effect by patterning boundary proximity in replacement metal gate

A method for fabricating a gate stack of a semiconductor device comprises forming a first dielectric layer over a channel region of the device, forming a first nitride layer over the first dielectric layer, forming a first gate metal layer over the first nitride layer, forming a capping layer over the first gate metal layer, removing portions of the capping layer and the first gate metal layer to expose a portion of the first nitride layer in a p-type field effect transistor (pFET) region of the gate stack, depositing a scavenging layer on the first nitride layer and the capping layer, depositing a second nitride layer on the scavenging layer, and depositing a gate electrode material on the second nitride layer.

Field effect transistor stack with tunable work function

Semiconductor devices include at least one semiconductor fin in each of a first region and a second region. A first work function stack that includes a bottom layer, a middle layer, and a top layer is formed over the at least one semiconductor fin in the first region. A second work function stack that includes a first layer and a second layer is formed over the at least one semiconductor fin in the second region. The first layer is continuous with the bottom layer of the first work function stack and the second layer is continuous with the middle layer of the first work function stack but has a smaller thickness than the middle layer. A continuous gate is formed over the first and the second work function stack.

A method of fabricating advanced multi-threshold field effect transistors using a replacement metal gate process. A first method includes thinning layers composed of multilayer film stacks and incorporating a portion of the remaining thinned film in some transistors. A second method includes patterning dopant materials for a high-k dielectric by using thinning layers composed of multilayer thin film stacks, or in other embodiments, by a single thinning layer.

Methods for making robust replacement metal gates and multi-threshold devices in a soft mask integration scheme

A method for fabricating a gate stack of a semiconductor device comprises forming a first dielectric layer over a channel region of the device, depositing a first nitride layer on exposed portions of the first dielectric layer, depositing a scavenging layer on the first nitride layer, forming a capping layer over the scavenging layer, removing portions of the capping layer, the scavenging layer, and the first nitride layer to expose a portion of the first dielectric layer in an n-type field effect transistor (nFET) region of the gate stack, forming a barrier layer over the first dielectric layer and the capping layer, forming a first gate metal layer over the barrier layer, depositing a second nitride layer on the first gate metal layer, and depositing a gate electrode material on the second nitride layer.

Field effect transistor gate stack

Embodiments of the present invention provide a process that maintains a 'keep cap' metal nitride layer on PFET devices within a CMOS structure. The keep cap metal nitride layer is in place while an N-type work function metal is formed on the NFET devices within the CMOS structure. A sacrificial rare earth oxide layer, such as a lanthanum oxide layer is used to facilitate removal of the n-type work function metal selective to the keep cap metal nitride layer.

Method and structure for formation of replacement metal gate field effect transistors

Semiconductor devices and methods of forming the same include forming a work function stack over semiconductor fins in a first region and a second region, the work function stack having a bottom layer, a middle layer, and a top layer. The work function stack is etched to remove the top layer and to decrease a thickness of the middle layer in the second region, leaving a portion of the middle layer and the bottom layer intact. A gate is formed over the semiconductor fins in the first and second regions.

Semiconductor structures and methods of fabricating the same using interrupted deposition processes and multiple laser anneals are provided. The structure includes a high-k gate stack with a high-k bilayer or nanolaminate where a bottom portion of the bilayer is crystallized while a top portion of the bilayer is amorphous.

Gate stack formed with interrupted deposition processes and laser annealing

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Fishkill, NY, United States of America

Unoh Kwon