Infineon Technologies Ag

Kabushiki Kaisha Toshiba

Other

Infineon Ag

Ulrich Egger

Haoren Zhuang

Karl Hornik

Kazuhiro Tomioka

Rainer Bruchhaus

Jenny Lian

Jingyu Lian

Hiroyuki Kanaya

Andreas Hilliger

Gerhard Beitel

Stefan Gernhardt

Nicolas Nagel

Yoshinori Kumura

Osamu Arisumi

Bum-ki Moon

Bum-Ki Moon

George Stojakovic

Yoshinoru Kumura

Haoran Zhuang

A semiconductor device according to an aspect of the invention includes a semiconductor substrate, and a capacitor that is provided above the semiconductor substrate and is configured such that a dielectric film is sandwiched between a lower electrode and an upper electrode, the dielectric film being formed of an ABOperovskite-type oxide that includes at least one of Pb, Ba and Sr as an A-site element and at least one of Zr, Ti, Ta, Nb, Mg, W, Fe and Co as a B-site element, wherein a radius of curvature of a sidewall of the capacitor, when viewed from above or in a film thickness direction, is 250 [nm] or less, and a length of an arc with the radius of curvature is {250 [nm]&#xd7;&#x3c0;/6 [rad]} or less.

Semiconductor device and mask pattern

Ferrocapacitors having a vertical structure are formed by a process in which a ferroelectric layer is deposited over an insulator. In a first etching stage, the ferroelectric material is etched to form openings in it, leaving the insulating layer substantially intact. Then a conductive layer is deposited into the openings formed in the ferroelectric layer, forming electrodes on the sides of the openings. Further etching is performed to form gaps in the AlOlayer, for making connections to conductive elements beneath it. Thus, by the time the second etching step is performed; there are already electrodes overlying the sides of the ferroelectric material, without insulating fences in between.

Method for forming ferrocapacitors and FeRAM devices

A method of etching a ferroelectric devicehaving a ferroelectric layerbetween a top and a bottom electrodeis disclosed herein. Hardmasksare deposited on the top electrode, two or more hardmasks being spaced apart by narrow first regionsand spaced apart from other hardmasks by wider second regions. The top electrodeand ferroelectric layerare then etched to pattern the top electrodethus forming capacitors, and the bottom electrodeis etched by a process in which the second regions are etched more slowly than the second regions. Those capacitors having a first region between them have a common bottom electrode, but in the second regions the bottom electrode is severed. To pattern the bottom electrode, a fluorine-based chemistry followed thereafter by a CO-based chemistry are used in a two step etching process.

Method of etching ferroelectric devices

A ferroelectric capacitor device comprises a substrate, a contact plug passing through the substrate, a first electrode formed on the substrate, the first electrode being electrically connected to said plug, a ferroelectric layer formed on the first electrode, a second electrode formed on the ferroelectric layer, one or more first encapsulation layers on the second electrode, the encapsulation layers extending over the device, and one or more hydrogen storage material layers on the encapsulation layers. One or more second encapsulation layers may be formed on the one or more hydrogen storage material layers.

Device for inhibiting hydrogen damage in ferroelectric capacitor devices

The present invention provides a ferroelectric device relatively free of fences by using a hardmask having high etching selectivity relative to an underlying barrier layer. The present invention also includes a method for suppressing the fences clinging to the sidewalls of ferroelectric devices. Additionally, the present invention provides a ferroelectric device having a hardmask relatively thin compared to an underlying barrier layer when compared to prior art devices.

Hardmask with high selectivity for Ir barriers for ferroelectric capacitor manufacturing

The present invention provides a sidewall oxygen diffusion barrier and a method for fabricating the sidewall oxygen diffusion barrier that reduces the diffusion of oxygen into contact plugs during a CW hole reactive ion etch of a ferroelectric capacitor of an FeRAM device. In one embodiment the sidewall barrier is formed from a substrate fence. In another embodiment, the sidewall barrier is formed by etching back an oxygen barrier.

Sidewall structure and method of fabrication for reducing oxygen diffusion to contact plugs during CW hole reactive ion etch processing

An Iridium barrier layer is between a contact plug and a bottom electrode of a capacitor. Etching is performed to pattern the bottom electrode and barrier layer using a fluorine-based recipe resulting in the formation of a first fence clinging to the sidewalls. Next the remaining barrier layer is etched using a CO-based recipe. A second fence is formed clinging to and structurally supported by the first fence. At the same time, the CO-based recipe etches away a substantial portion of the first fence to remove the structural support provided to the second fence. The second fence is therefore lifted-off from the sidewalls leaving the sidewalls substantially free of clinging fences. The etched barrier layer has a sidewall transition. The sidewalls have a relatively low taper angle above the sidewall transition and a relatively steep taper angle below the sidewall transition.

Fence-free etching of iridium barrier having a steep taper angle

A method for fabricating a device and a device, such as a ferroelectric capacitor, having a substrate, a contact plug through the substrate, a first barrier layer on the substrate, a first electrode on the first barrier layer, a dielectric layer on the first electrode, and a second electrode on the dielectric layer, comprises etching the second electrode and the dielectric layer of the device using a first hardmask, to shape the second electrode and the dielectric layer. The first hardmask is then removed and one or more encapsulating layers are applied to the second electrode and the dielectric layer. A further hardmask is applied to the one or more encapsulating layers. The first electrode is then etched according to the second hardmask down to the first barrier layer and the second hardmask is then removed from the one or more encapsulating layers.

Method for producing a ferroelectric capacitor that includes etching with hardmasks

A ferroelectric device includes a bottom electrode on which are formed ferrocapacitor elements and, over the ferroelectric elements, top electrodes. The bottom electrodes are connected to lower layers of the device via conductive plugs, and the plugs and bottom electrodes are spaced apart by barrier elements of Ir and/or IrO. The barrier elements are narrower than the bottom electrode elements, and are formed by a separate etching process. This means that Ir fences are not formed during the etching of the bottom electrode. Also, little Ir and/or IrOdiffuses through the bottom electrode to the ferroelectric elements, and therefore there is little risk of damage to the ferroelectric material.

Method of fabrication of an FeRAM capacitor and an FeRAM capacitor formed by the method

A ferroelectric capacitor device, such as an FeRAM device is formed by forming a substrate extending in a first plane and comprising a number of layers of material, forming a hard mask layer on the substrate and forming a first layer of a first material on the hard mask layer. The hard mask shape is then defined by etching the hard mask layer. A second layer of the first material is deposited on the etched hard mask layer. The deposited second layer has one or more side surfaces extending substantially perpendicular to the plane of the substrate. The second layer and the number of layers forming the substrate are then etched to shape the ferroelectric capacitor device.

Method for forming a ferroelectric capacitor device

A capacitor structure having a capacitor with a top electrode, a bottom electrode, and a capacitor dielectric layer between the top and bottom electrodes is disclosed. The capacitor includes upper and lower portions. The demarcation between the upper and lower portion is located between top and bottom surfaces of the capacitor dielectric layer. A dielectric layer is provided on the sidewalls of the upper portion of the capacitor to prevent shorting between the electrodes that can be caused by a conductive fence formed during processing.

Avoiding shorting in capacitors

A ferroelectric capacitor is fabricated using a noble metal hardmask. A hardmask is deposited on a top electrode of a capacitor stack comprising a ferroelectric layer sandwiched between the top electrode and a bottom electrode. The top electrode is patterned according to the pattern of the hardmask by etching at a first temperature. The top electrode serves as the noble metal hardmask and the ferroelectric layer is patterned according to the pattern of the top electrode at a second temperature lower than the first temperature, resulting in the top electrode having sidewalls beveled relative to a top surface of the top electrode etching. The bottom electrode is etched at a third temperature to form the capacitor.

Fabrication of a FeRAM capacitor using a noble metal hardmask

Forming a capacitor, by (a) forming a matrix of ferroelectric capacitor elements on a substrate, (b) forming a CAP layer over the ferroelectric capacitor elements, and (c) etching the CAP layer to a more uniform thickness. A capacitor that has a substrate layer, a matrix of ferroelectric capacitor elements including a first electrode layer substantially fixed relative to the substrate, a second electrode layer, and a ferroelectric layer sandwiched between the first and second electrode layers is disclosed. The capacitor has a shoulder layer extending from the substrate to the matrix, and a CAP layer etched to have substantially constant thickness covering sides of the matrix extending beyond the substrate.

Ferroelectric capacitor and process for its manufacture

A process for the fabrication of a ferrocapacitor comprising depositing a first mask element over a structure having a bottom electrode , a ferroelectric layer and a top electrode . RIE etching is performed to remove portions of the top electrode and the ferroelectric layer . Then a second hard mask element is deposited over the first hardmask element. The second hard mask element is rounded by an etch back process, and its taper angle is controlled to be in the range 75-87&deg;. A second RIE etching process is performed to remove portions of the bottom electrode . Due to the rounding of the second hard mask elements low residues are formed on the sides of the etched bottom electrode

Process for fabrication of a ferrocapacitor

A ferroelectric capacitor encapsulation method for preventing hydrogen damage to electrodes and ferroelectric material of the capacitor. In general terms, the method for encapsulating a capacitor includes etching a bottom electrode of a capacitor to expose an underlying wafer surface. An undercut is etched between the capacitor and the wafer surface. The undercut is refilled with a barrier layer to reduce the diffusion of hydrogen from the surface of the wafer into the capacitor.

Growing community of inventors

Kanagawa-ken, Japan

Ulrich Egger