Taiwan Semiconductor Manufacturing Comp. Ltd.

Tzu-Yang Ho

Tze-Liang Lee

Jr-Hung Li

Tsai-Jung Ho

Huicheng Chang

Liang-Yin Chen

Su-Hao Liu

Kuo-Ju Chen

Pei-Yu Chou

Meng-Han Chou

Mei-Yun Wang

Fu-Kai Yang

Chen-Ming Lee

Shih-Che Lin

A semiconductor device and a method of forming the same are provided. The semiconductor device includes a substrate, a gate structure, a dielectric structure and a contact structure. The substrate has source/drain (S/D) regions. The gate structure is on the substrate and between the S/D regions. The dielectric structure covers the gate structure. The contact structure penetrates through the dielectric structure to connect to the S/D region. A lower portion of a sidewall of the contact structure is spaced apart from the dielectric structure by an air gap therebetween, while an upper portion of the sidewall of the contact structure is in contact with the dielectric structure.

Methods of forming semiconductor device

A method may include forming a first silicon nitride layer in an opening of the semiconductor device and on a top surface of the semiconductor device, wherein the semiconductor device includes an epitaxial source/drain and a metal gate. The method may include forming a second silicon nitride layer on the first silicon nitride layer, as a sacrificial layer, and removing the second silicon nitride layer from sidewalls of the first silicon nitride layer formed in the opening. The method may include removing the second silicon nitride layer and the first silicon nitride layer formed at a bottom of the opening, and depositing a metal layer in the opening to form a metal drain in the opening of the semiconductor device.

Topology selective and sacrificial silicon nitride layer for generating spacers for a semiconductor device drain

A semiconductor device structure, along with methods of forming such, are described. The semiconductor device structure includes a gate electrode layer disposed over a substrate, a source/drain epitaxial feature disposed over the substrate, a first hard mask layer disposed over the gate electrode layer, and a contact etch stop layer (CESL) disposed over the source/drain epitaxial feature. The structure further includes a first interlayer dielectric (ILD) layer disposed on the CESL and a first treated portion of a second hard mask layer disposed on the CESL and the first ILD layer. A top surface of the first hard mask layer and a top surface of the first treated portion of the second mask layer are substantially coplanar. The structure further includes an etch stop layer disposed on the first hard mask layer and the first treated portion of the second mask layer.

Semiconductor device structure and methods of forming the same

Semiconductor device and methods of forming the same

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Hsinchu, Taiwan

Tzu-Yang Ho