Taiwan Semiconductor Manufacturing Comp. Ltd.

Tzu-Wei Chiu

Shin-Puu Jeng

Shang-Yun Hou

Kuo-Ching Hsu

Wei-Cheng Wu

Hsien-Pin Hu

Tzu-Yu Wang

Cheng-Hsien Hsieh

Sao-Ling Chiu

Tzuan-Horng Liu

Chen-Hua Douglas Yu

Hsien-Wei Chen

Hung-An Teng

Chao-Wen Shih

Chun-Yi Liu

Embodiments of the present disclosure include a semiconductor device and methods of forming a semiconductor device. An embodiment is a semiconductor device comprising an interconnecting structure consisting of a plurality of thin film layers and a plurality of metal layers disposed therein, each of the plurality of metal layers having substantially a same top surface area, and a die comprising an active surface and a backside surface opposite the active surface, the active surface being directly coupled to a first side of the interconnecting structure. The semiconductor device further comprises a first connector directly coupled to a second side of the interconnecting structure, the second side being opposite the first side.

3D packages and methods for forming the same

A method comprises embedding a semiconductor structure in a molding compound layer, depositing a plurality of photo-sensitive material layers over the molding compound layer, developing the plurality of photo-sensitive material layers to form a plurality of openings, wherein a first portion and a second portion of an opening of the plurality of openings are formed in different photo-sensitive material layers and filling the first portion and the second portion of the opening with a conductive material to form a first via in the first portion and a first redistribution layer in the second portion.

Fan-out package structure and method

A device comprises a semiconductor structure in a molding compound layer, a first polymer layer on the molding compound layer, a second polymer layer on the first polymer layer, a first interconnect structure having a first via portion in the first polymer layer and a first metal line portion in the second polymer layer, a third polymer layer on the second polymer layer, a fourth polymer layer on the third polymer layer and a second interconnect structure having a second via portion in the third polymer layer and a second metal line portion in the fourth polymer layer, wherein the second via portion is vertically aligned with the first via portion.

A bump structure for electrically coupling semiconductor components is provided. The bump structure includes a first bump on a first semiconductor component and a second bump on a second semiconductor component. The first bump has a first non-flat portion (e.g., a convex projection) and the second bump has a second non-flat portion (e.g., a concave recess). The bump structure also includes a solder joint formed between the first and second non-flat portions to electrically couple the semiconductor components.

Bump structure for yield improvement

A method includes attaching a semiconductor structure on a carrier, depositing a molding compound layer over the carrier, wherein the semiconductor structure is embedded in the molding compound layer, exposing a first photo-sensitive material layer and a second photo-sensitive material layer to light, developing the first photo-sensitive material layer and the second photo-sensitive material layer to form an opening having a first portion in the first photo-sensitive material layer and a second portion in the second photo-sensitive material layer, wherein a width of the second portion is greater than a width of the first portion, filling the opening with a conductive material to form a via in the first photo-sensitive material layer and a redistribution layer in the second photo-sensitive material layer and forming a bump over the redistribution layer.

A packaged IC chip includes a testing pad, wherein the testing pad is electrically connected to devices in the packaged integrated circuit chip. The packaged IC chip further includes a first passivation layer over a portion of the testing pad, and a second passivation layer covering a surface of the testing pad and a portion of the first passivation layer surrounding the testing region of the testing pad. A distance between edges of the second passivation layer covering the surface of the testing pad to edges of the testing pad is in a range from about 2 mm to about 15 mm.

Passivation layer for packaged chip

A semiconductor device includes a bonding pad on a substrate. The semiconductor device further includes a passivation layer covering a peripheral portion of the bonding pad while exposing a middle portion of the bonding pad. Additionally, the semiconductor device includes a stress buffer layer over the passivation layer where the stress buffer layer exposes a portion of the bonding pad, and where a wall of the stress buffer layer extends, in steps, upwardly from the exposed portion of the bonding pad. Furthermore, the semiconductor device includes an under-bump metallurgy (UBM) layer over the stress buffer layer, where the UBM layer contacts a portion of the bonding pad.

Stress buffer structures in a mounting structure of a semiconductor device

A mounting structure for a semiconductor device is formed to include a stepwise stress buffer layer under a stepwise UBM structure.

Growing community of inventors

Hsinchu, Taiwan

Tzu-Wei Chiu